computing

The rise of Artificial Intelligence (AI) and Machine Learning (ML) has rapidly impacted today's global economy, influencing everything from healthcare to autonomous systems. As of 2023, 55% of organizations used AI in at least one business unit or function, compared to only 20% in 2017 [1].As it permeates more of our economies and daily lives, AI extends beyond the technical. Every country around the world needs to work out their strategy to unlock the potential of AI to solve local problems, while also being able to access the possibilities of a worldwide market. Now, as nations rush to harness the power of AI, it has become clear that the development of robust, performant, and efficient AI/ML computing resources is a global necessity.&nbsp;Enabling widespread access to AI/ML hardware and software is now a matter of global importance. RISC-V is a proven player in this effort. In this article, we’ll explore how RISC-V can transform the AI/ML sector, promote consensus-driven development and global collaboration, and bring socioeconomic benefits to countries around the world.<h1 dir="ltr">Improving Programmer Productivity With a Unified Model</h1>A unique aspect of RISC-V is its unified programming model, which enables the customized development of different types of processors, CPU, GPU and NPU, under a single, consistent set of instructions and interfaces. The model provides programmers with a standardized framework and common tools that enable them to easily write versatile and efficient code across different processing units.&nbsp;Through the use of a single architecture [2], RISC-V eliminates the need for separate programming paradigms for different processing units. As such, RISC-V reduces the learning curve and minimizes the overhead associated with switching between different architectures. Ultimately, this simplifies coding efficiency, reduces errors, and accelerates development cycles.The enhanced productivity facilitated by RISC-V can lead to a competitive edge in technological advancements. Global economies that embrace RISC-V can expedite their custom AI/ML developments to solve local problems and strengthen their positions in the global tech landscape through the adoption of the RISC-V standard. Ideally, this advantage translates into economic growth, job creation, and increased influence in the digital economy.Socioeconomically, RISC-V reduces barriers to entry for AI/ML development and democratizes access to advanced computing capabilities. Such democratization helps to encourage local innovation with worldwide impact across diverse sectors, driving societal progress, and improving quality of life.<h1 dir="ltr">Encouraging International Collaboration</h1>RISC-V is transforming the computing landscape by encouraging unprecedented levels of international collaboration [3].&nbsp;Specifically, the RISC-V industry standard Instruction Set Architecture (ISA) removes proprietary barriers, allowing developers, companies, and academic institutions worldwide to contribute to and benefit from the RISC-V architecture. In contrast to proprietary ISAs, where mainly major players have significant influence, RISC-V allows innovation to emerge from anywhere. It empowers smaller entities and individual contributors to take a first-hand approach in the technological revolution, resulting in a more equitable and dynamic technological ecosystem.The net effect of this openness is the fostering of a global community of innovators, all working cohesively to drive collaborative research and development across borders. By leveraging the collective intelligence and diverse perspectives of an international cohort, RISC-V presents an unprecedented opportunity to accelerate technological advancements in AI. Ultimately, the consensus-driven nature of RISC-V ensures that improvements and innovations are shared broadly.RISC-V is also unique in that, by adhering to a common set of standards, it enables unprecedented ease of integration and interoperability among hardware and software developed by different entities worldwide. As a result, companies, governments, universities and developers can work together more effectively, pooling their resources and expertise to tackle complex challenges collectively and push the state of the industry forward.&nbsp;The implications of this collaborative approach are significant. Nations that embrace RISC-V can enhance their technological capabilities through shared knowledge and resources. Brazil, for example, is developing AI infrastructure based on RISC-V, focused on High-Performance Computing (HPC), semiconductor technology, and large language models [4]. Such a collaborative spirit can lead to stronger international alliances and partnerships and drive economic growth and technological progress on a global scale.&nbsp;<h1 dir="ltr">Breaking Vendor Lock-In</h1>Finally, one of RISC-V’s most important value propositions is that it introduces a new paradigm in which developers and companies have a wider range of choices for AI processing. Namely, the RISC-V ISA enables the design and implementation of custom processors, and also for the RISC-V semiconductor ecosystem to develop a wider range of pre-developed AI chips to choose from. Expertise and technologies from the RISC-V ecosystem of members can support any development, with a breadth of choice that also prevents your choice of AI vendor creating a long term dependency. &nbsp;By eliminating vendor lock-in, RISC-V enables developers to work faster, be more creative, and explore more flexible and rapid development cycles. RISC-V can further support the development and use of advanced technologies without restrictions on innovation. Where the goal is to create an equitable AI/ML landscape, RISC-V can help regions innovate independently, foster local talent, and establish a robust technological infrastructure that supports long-term growth and sustainability, while also maintaining access to a global market and ecosystem of partners.The benefits of breaking vendor lock-in extend significantly to the automotive industry, for example, which is currently undergoing its own set of transformations. Here, RISC-V offers the flexibility needed to innovate and remain competitive on a global scale. As cars become more and more defined by software workloads, including increased use of AI, manufacturers can leverage RISC-V to develop bespoke hardware solutions tailored to the specific needs of their markets [5], ensuring they keep pace with or even surpass their global competitors.&nbsp;Overall, by freeing the industry from vendor lock-in, RISC-V can give developers worldwide, and &nbsp;regions like Europe and Brazil, the tools needed to lead technological innovation and develop true digital sovereignty.&nbsp;<h1 dir="ltr">Conclusion&nbsp;</h1>The modern emergence of AI/ML is more than a simple technical phenomenon; it’s a movement with significant worldwide implications. As nations strive for digital sovereignty, RISC-V offers the tools needed to build robust, independent technological infrastructures while also enabling access to a global market and ecosystem of partner expertise.RISC-V is truly a catalyst for an equitable and collaborative future in AI and ML. As the importance of global deployment of AI/ML continues to grow, RISC-V will undoubtedly have a major role to play in the future of computing around the world.&nbsp;<h1 dir="ltr">References</h1>[1] <a href="https://aiindex.stanford.edu/report/" target="_blank">https://aiindex.stanford.edu/report/</a>[2]&nbsp;<a href="https://riscv.org/technical/specifications/" target="_blank">https://riscv.org/technical/specifications/</a>&nbsp;[3]<a href="https://riscv.org/blog/2023/10/risc-v-an-open-standard-backed-by-a-global-community-to-enable-open-computing-for-all/" target="_blank">https://riscv.org/blog/2023/10/risc-v-an-open-standard-backed-by-a-global-community-to-enable-open-computing-for-all/</a>[4]<a href="https://riscv.org/blog/2024/09/advancing-ai-the-brazilian-way-fostering-innovation-through-collaboration-and-open-standards/" target="_blank">https://riscv.org/blog/2024/09/advancing-ai-the-brazilian-way-fostering-innovation-through-collaboration-and-open-standards/</a>&nbsp;[5]<a href="https://riscv.org/blog/2024/08/infineon-harness-the-power-of-risc-v-for-next-generation-automotive-mcu-innovation/" target="_blank">https://riscv.org/blog/2024/08/infineon-harness-the-power-of-risc-v-for-next-generation-automotive-mcu-innovation/</a>

RISC-V offers the tools needed to foster local AI innovation while also enabling worldwide collaboration and access to a global market 

How RISC-V Changes the Global Landscape of AI and ML

A GPU microchip for accelerated AI processing

Unleashing the Power of GPU, understanding the essential strategies for efficient Deep Learning Model Training without compromising on memory and hardware resources in Graphical Processing Units

Maximize GPU Utilization for Model Training: Unlocking Peak Performance

When we think of&nbsp;fleet&nbsp;management&nbsp;our&nbsp;thoughts tend to turn towards the major transport&nbsp;and&nbsp;logistics&nbsp;companies,&nbsp;and the enormous fleets of vehicles they&nbsp;must&nbsp;keep&nbsp;a track&nbsp;of&nbsp;across the supply chain.&nbsp;But even the world’s biggest trucking company, United Parcel Service (UPS),&nbsp;that&nbsp;operates&nbsp;more than 340,000 vehicles&nbsp;across some 200&nbsp;countries[1],&nbsp;has a&nbsp;miniscule&nbsp;‘fleet’&nbsp;compared with&nbsp;the&nbsp;17&nbsp;billion[2]&nbsp;or so connected IoT devices that are currently employed in countless different industries, including in UPS’ own trucks.&nbsp;Billions of these devices are also deployed in fleets by the companies that service them, in practically limitless applications. It might be vending machines, medical devices, EV charging stations, or any of the smart sensors, actuators or monitoring devices installed in smart cities around the world. But deployment is just the first step, these fleets of IoT devices can’t just be launched into the wild and then forgotten about. Any IoT device fleet must be managed throughout its lifecycle to ensure effective and secure operation as well as adequate maintenance and updates, and to achieve that they require robust, stable IoT device management from the Cloud. &nbsp;&nbsp;<h2>IoT device&nbsp;data&nbsp;management&nbsp;and security</h2>Throughout the lifecycle of an IoT device—from provisioning to decommissioning—various management tasks are essential, and chief among them is data management. A fleet of IoT devices are essentially an army of data collectors, and while local processing can be efficient, it has limited scope. Sending data to the Cloud enables that data to be analyzed at scale and in near real time, driving value to the IoT device fleet owner.&nbsp;<a href="https://www.nordicsemi.com/Products/Cloud-services/Device-Management" target="_blank">Cloud-based device management</a>&nbsp;also ensures the data continues to flow without any problems.&nbsp;&nbsp;The second reason IoT devices need Cloud device management is for security. On average, every week 54 percent of organizations suffer from attempted cyber-attacks targeting IoT devices[3]. It’s an alarming statistic and highlights the need for vigilance to protect devices and data from unauthorized access and attacks. Regular firmware updates make it easier to keep devices secure, bug-free, up-to-date with new features, and capable of adapting to evolving requirements throughout their lifecycle. For the majority of IoT devices this can’t be performed via physical access or manual intervention, so the ability to execute firmware over-the-air (FOTA) updates from the Cloud is essential.&nbsp;&nbsp;<h2>Performance, scalability,&nbsp;and compliance</h2>In addition to data management and security, Cloud-based IoT device management can assist with performance, scalability, and compliance requirements. Identifying and addressing performance issues remotely and as quickly as possible not only ensures devices are operating at their full potential, but it can also greatly reduce the cost of ongoing maintenance. And as the number of IoT devices grows, deploying and managing large fleets can become a significant challenge. Certain operations for masses of devices should always be done simultaneously and a Cloud device management platform simplifies this process across different devices and applications.&nbsp;&nbsp;Finally, IoT device operators must ensure all ongoing regulatory and compliance requirements have been fulfilled, and a Cloud device management platform can ensure compliance by enforcing policies, maintaining audit trails, and facilitating reporting and documentation as may be required.&nbsp;&nbsp;<h2>One-stop solution for the IoT</h2>This growing demand for a flexible and scalable Cloud device management platform was behind the expansion of Nordic Semiconductor’s&nbsp;<a href="https://www.nordicsemi.com/Products/Cloud-services" target="_blank">Cloud Services</a>&nbsp;offering earlier this year to include&nbsp;<a href="https://www.nordicsemi.com/Products/Cloud-services/Device-Management?lang=en#infotabs" target="_blank">nRF Cloud Device Management</a>&nbsp;alongside the existing&nbsp;<a href="https://www.nordicsemi.com/Products/Cloud-services/Location-Services?lang=en#infotabs" target="_blank">location</a>&nbsp;and&nbsp;<a href="https://www.nordicsemi.com/Products/Cloud-services/Security-Services?lang=en#infotabs" target="_blank">security</a>&nbsp;services provided in the&nbsp;<a href="https://nrfcloud.com/?__hstc=8439722.f1ebab9b9306be644289de1432e134ad.1698403132381.1725606365510.1726203396952.45&__hssc=8439722.2.1726203396952&__hsfp=1429543644#/" target="_blank">nRF Cloud</a>&nbsp;suite. The launch marks the first time IoT developers and businesses have had a one-stop solution (hardware, software, and Cloud services) for the deployment and management of IoT devices at scale.&nbsp;nRF Cloud Device Management provides tools for onboarding, configuration, monitoring, and FOTA updates, as well as for comprehensive management of IoT device fleets across their lifecycle. The tools also facilitate sensor data collection services and enable technicians to ensure that fleets remain up-to-date and operate at peak efficiency. Together with the complementary location and security services, it promises developers the perfect quartet of IoT deployment requirements – reduced time-to-market, scalability, future proofing, and cost savings.<hr>References:&nbsp; 1. <a href="https://www.fleetequipmentmag.com/fleet-profile-ups-shares-results-of-strong-investment-in-alternative-fuel/" target="_blank">UPS shares results of strong investment in alternative fuel</a>.&nbsp;Fleet Equipment Magazine, January 2024 2. <a href="https://transformainsights.com/research/reports/global-iot-forecast-report-2023-2033" target="_blank">Global IoT Forecast Report, 2022-2033</a>.&nbsp;Transforma Insights, May 2024 3. <a href="https://blog.checkpoint.com/security/the-tipping-point-exploring-the-surge-in-iot-cyberattacks-plaguing-the-education-sector/" target="_blank">The Tipping Point: Exploring the Surge in IoT Cyberattacks Globally</a>. Check Point Research, April 2023&nbsp;

When we think of fleet management our thoughts tend to turn towards the major transport and logistics companies, and the enormous fleets of vehicles they must keep a track of across the supply chain.

Managing IoT Devices from the Cloud

Imagine how a phone call works: Your voice is converted into electronic signals, shifted up to higher frequencies, transmitted over long distances, and then shifted back down so it can be heard clearly on the other end. The process enabling this shifting of signal frequencies is called frequency mixing, and it is essential for communication technologies like radio and Wi-Fi. Frequency mixers are vital components in many electronic devices and typically operate using frequencies that oscillate billions (GHz, gigahertz) to trillions (THz, terahertz) of times per second.&nbsp;Now imagine a frequency mixer that works at a quadrillion (PHz, petahertz) times per second — up to a million times faster. This frequency range corresponds to the oscillations of the electric and magnetic fields that make up light waves.&nbsp;Petahertz-frequency mixers would allow us to shift signals up to optical frequencies and then back down to more conventional electronic frequencies, enabling the transmission and processing of vastly larger amounts of information at many times higher speeds. This leap in speed isn’t just about doing things faster; it’s about enabling entirely new capabilities.Lightwave electronics (or petahertz electronics) is an emerging field that aims to integrate optical and electronic systems at incredibly high speeds, leveraging the ultrafast oscillations of light fields. The key idea is to harness the electric field of light waves, which oscillate on sub-femtosecond (10-15&nbsp;seconds) timescales, to directly drive electronic processes. This allows for the processing and manipulation of information at speeds far beyond what is possible with current electronic technologies. In combination with other petahertz electronic circuitry, a petahertz electronic mixer would allow us to process and analyze vast amounts of information in real time and transfer larger amounts of data over the air at unprecedented speeds. The MIT team’s demonstration of a lightwave-electronic mixer at petahertz-scale frequencies is a first step toward making communication technology faster, and progresses research toward developing new, miniaturized lightwave electronic circuitry capable of handling optical signals directly at the nanoscale.In the 1970s, scientists began exploring ways to extend electronic frequency mixing into the terahertz range using diodes. While these early efforts showed promise, progress stalled for decades. Recently, however, advances in nanotechnology have reignited this area of research. Researchers discovered that tiny structures like nanometer-length-scale needle tips and plasmonic antennas could function similarly to those early diodes but at much higher frequencies.A recent open-access&nbsp;<a href="https://www.science.org/doi/10.1126/sciadv.adq0642" target="_blank">study published in&nbsp;Science Advances</a> by Matthew Yeung, Lu-Ting Chou, Marco Turchetti, Felix Ritzkowsky, Karl K. Berggren, and Phillip D. Keathley at MIT has demonstrated a significant step forward. They developed an electronic frequency mixer for signal detection that operates beyond 0.350 PHz using tiny nanoantennae. These nanoantennae can mix different frequencies of light, enabling analysis of signals oscillating orders of magnitude faster than the fastest accessible to conventional electronics. Such petahertz electronic devices could enable developments that ultimately revolutionize fields that require precise analysis of extremely fast optical signals, such as spectroscopy and imaging, where capturing femtosecond-scale dynamics is crucial (a femtosecond is one-millionth of one-billionth of a second).The team’s study highlights the use of nanoantenna networks to create a broadband, on-chip electronic optical frequency mixer. This innovative approach allows for the accurate readout of optical wave forms spanning more than one octave of bandwidth. Importantly, this process worked using a commercial turnkey laser that can be purchased off the shelf, rather than a highly customized laser.While optical frequency mixing is possible using nonlinear materials, the process is purely optical (that is, it converts light input to light output at a new frequency). Furthermore, the materials have to be many wavelengths in thickness, limiting the device size to the micrometer scale (a micrometer is one-millionth of a meter). &nbsp;In contrast, the lightwave-electronic method demonstrated by the authors uses a light-driven tunneling mechanism that offers high nonlinearities for frequency mixing and direct electronic output using nanometer-scale devices (a nanometer is one-billionth of a meter).While this study focused on characterizing light pulses of different frequencies, the researchers envision that similar devices will enable one to construct circuits using light waves. This device, with bandwidths spanning multiple octaves, could provide new ways to investigate ultrafast light-matter interactions, accelerating advancements in ultrafast source technologies.&nbsp;This work not only pushes the boundaries of what is possible in optical signal processing but also bridges the gap between the fields of electronics and optics. By connecting these two important areas of research, this study paves the way for new technologies and applications in fields like spectroscopy, imaging, and communications, ultimately advancing our ability to explore and manipulate the ultrafast dynamics of light.The research was initially supported by the U.S. Air Force Office of Scientific Research. Ongoing research into harmonic mixing is based upon work supported by the U.S. Department of Energy, Office of Science, Office of Basic Energy Sciences. Matthew Yeung acknowledges fellowship support from MathWorks, the U.S. National Science Foundation Graduate Research Fellowship Program, and MPS-Ascend Postdoctoral Research Fellowship. Lu-Ting Chou acknowledges financial support from the China's Ministry of Education for the Overseas Internship Program from the Chinese National Science and Technology Council for the doctoral fellowship program. This work was carried out, in part, through the use of MIT.nano.

The demonstration of a lightwave-electronic mixer at petahertz-scale frquencies is a first step toward making communication technology faster and progresses research toward developing new, miniaturized lightwave electronic circuitry capable of handling optical signals directly at the nanoscale. Image: Sampson Wilcox/Research Laboratory of Electronics

Lightwave electronics aim to integrate optical and electronic systems at incredibly high speeds, leveraging the ultrafast oscillations of light fields.

Nanostructures enable on-chip lightwave-electronic frequency mixer

Curious about Data Warehouse, Data Lake, and Data Lakehouse? This article breaks down their key differences and how they impact decisions on managing big data. Learn how these solutions shape industries and drive smarter data strategies.

Data Warehouse Vs Data Lake Vs Data Lakehouse: Navigating the Modern Data Storage Landscape

Phase separation, when molecules part like oil and water, works alongside oxygen diffusion to help memristors—electrical components that store information using electrical resistance—retain information even after the power is shut off, according to a University of Michigan led study recently published in Matter.Up to this point, explanations have not fully grasped how memristors retain information without a power source, known as nonvolatile memory, because models and experiments do not match up.“While experiments have shown devices can retain information for over 10 years, the models used in the community show that information can only be retained for a few hours,” said Jingxian Li, U-M doctoral graduate of materials science and engineering and first author of the study.To better understand the underlying phenomenon driving nonvolatile memristor memory, the researchers focused on a device known as resistive random access memory or RRAM, an alternative to the volatile RAM used in classical computing, and are particularly promising for energy-efficient artificial intelligence applications.&nbsp;The specific RRAM studied, a filament-type valence change memory (VCM), sandwiches an insulating tantalum oxide layer between two platinum electrodes. When a certain voltage is applied to the platinum electrodes, a conductive filament forms a tantalum ion bridge passing through the insulator to the electrodes, which allows electricity to flow, putting the cell in a low resistance state representing a “1” in binary code. If a different voltage is applied, the filament is dissolved as returning oxygen atoms react with the tantalum ions, “rusting” the conductive bridge and returning to a high resistance state, representing a binary code of “0”.&nbsp;It was once thought that RRAM retains information over time because oxygen is too slow to diffuse back. However, a series of experiments revealed that previous models have neglected the role of phase separation.&nbsp;“In these devices, oxygen ions prefer to be away from the filament and will never diffuse back, even after an indefinite period of time. This process is analogous to how a mixture of water and oil will not mix, no matter how much time we wait, because they have lower energy in a de-mixed state,” said&nbsp;<a href="https://mse.engin.umich.edu/people/yiyangli" target="_blank" rel="noreferrer noopener">Yiyang Li</a>, U-M assistant professor of materials science and engineering and senior author of the study.To test retention time, the researchers sped up experiments by increasing the temperature. One hour at 250°C is equivalent to about 100 years at 85°C—the typical temperature of a computer chip.Using the extremely high-resolution imaging of atomic force microscopy, the researchers imaged filaments, which measure only about five nanometers or 20 atoms wide, forming within the one micron wide RRAM device. &nbsp;“We were surprised that we could find the filament in the device. It’s like finding a needle in a haystack,” Li said.&nbsp;The research team found that different sized filaments yielded different retention behavior. Filaments smaller than about 5 nanometers dissolved over time, whereas filaments larger than 5 nanometers strengthened over time. The size-based difference cannot be explained by diffusion alone.Together, experimental results and models incorporating thermodynamic principles showed the formation and stability of conductive filaments depend on phase separation.&nbsp;The research team leveraged phase separation to extend memory retention from one day to well over 10 years in a rad-hard memory chip—a memory device built to withstand radiation exposure for use in space exploration.&nbsp;Other applications include in-memory computing for more energy efficient AI applications or memory devices for electronic skin—a stretchable electronic interface designed to mimic the sensory capabilities of human skin. Also known as e-skin, this material could be used to provide sensory feedback to prosthetic limbs, create new wearable fitness trackers or help robots develop tactile sensing for delicate tasks.“We hope that our findings can inspire new ways to use phase separation to create information storage devices,” Li said.Researchers at Ford Research, Dearborn; Oak Ridge National Laboratory; University at Albany; NY CREATES; Sandia National Laboratories; and Arizona State University, Tempe contributed to this study.The device was built in the&nbsp;<a href="https://lnf.engin.umich.edu/" target="_blank" rel="noreferrer noopener">Lurie Nanofabrication Facility</a> and studied at the&nbsp;<a href="https://mc2.engin.umich.edu/" target="_blank" rel="noreferrer noopener">Michigan Center for Materials Characterization</a>. The work at the University of Michigan was primarily funded by the National Science Foundation (ECCS-2106225).

Newly discovered role of phase separation can help develop memory devices for energy-efficient AI computing.

Solving a memristor mystery to develop efficient, long-lasting memory devices

Weighing Latency, Privacy, and Scalability to Optimize Your AI Strategy

The Convergence of Edge AI and Cloud: Making the Right Choice for Your AI Strategy

<h2 id="isPasted"><iframe id="66c33d8585cc0ed55e5ec302" width="250" class="specs-iframe" height="440" src="https://wevolver.com/iframe/specs/renesas-electronics-ra8m1-voice-kit?iframe=true" frameborder="0" scrolling="no" data-lf-form-tracking-inspected-kn9eq4roawkarlvp="true" data-lf-yt-playback-inspected-kn9eq4roawkarlvp="true" data-lf-vimeo-playback-inspected-kn9eq4roawkarlvp="true"></iframe>Enhancing Security Using the Latest Technology</h2>Security is a topic on everyone’s minds today, and as technology gets more advanced, it can be easier to bypass the older systems that others have built. Large-scale system hacks are highly publicized and can affect a wide range of people, but smaller scale hacks can be just as devastating. Therefore, it’s essential to use the best technology to protect what matters most, such as your home and family. Face recognition can provide a more effective home security solution than traditional keys and keypads. Physical keys can be duplicated, stolen, lost, or forgotten, and key codes can be guessed, forgotten, or shared with unauthorized users. Accurate face recognition technology has none of those disadvantages, and owners can easily manage the authorization of each person and log their entries.With some of these legacy security systems becoming easier to bypass, we need to constantly develop new solutions using the latest technology to keep the highest level of security. This is where the smart door lock, utilizing machine learning and 3D facial recognition from AMD technology partner Makarena Labs, comes into play. In this blog, we discuss how smart door technology is bringing peace of mind to the front door and more with a superior level of security.<h2>Addressing Current Security Problems in Smart Door Locks</h2>Smart door locks can provide increased protection for homes and other consumer dwelling spaces, like garages or sheds, but previous versions of smart locks can be easily tricked. Due to the incorporated technology—generally a standard CMOS sensor—previous smart locks can be fooled into opening by using 2D pictures of an authorized person’s face. This results in a false recognition and the system will allow an unauthorized person entry, which is a major security breach that needs to be addressed. &nbsp;AMD, in partnership with Makarena, have developed a capable solution, based on the AMD <a href="https://www.mouser.com/new/xilinx/xilinx-zynq-7000-socs/" target="_blank">Zynq™ 7000 SoC</a>, that provides a fully functional and robust design using 3D facial recognition. This advanced facial recognition is achieved through a camera that uses IR Time-of-Flight (TOF) or Lidar technology to bounce a pattern off the face of the person attempting to gain entry, while the sensors in the smart lock capture the reflection (Figure 1).<img src="https://images.wevolver.com/eyJidWNrZXQiOiJ3ZXZvbHZlci1wcm9qZWN0LWltYWdlcyIsImtleSI6ImZyb2FsYS8xNzI1ODUzMjUwMjExLUZpZ3VyZV8xX01ha2FyZW5hX0xhYnNfU21hcnRfTG9jay5wbmciLCJlZGl0cyI6eyJyZXNpemUiOnsid2lkdGgiOjk1MCwiZml0IjoiY292ZXIifX19" style="width: 100%px;" class="fr-fic fr-dib">Figure 1: This smart lock design, developed by AMD and their partner Makarena, is based on the AMD Zynq 7000 SoC, incorporates IR TOF or Lidar technology to detect and create a 3D map of the face, and compares the 3D map to the authorized users in the system, only unlocking if a match is found. (Source: AMD)Using the reflection captured by the sensors, the system creates a 3D map of the face and compares it to the authorized users in the system, only unlocking if a match is found (Figure 2). The CMOS sensor provides an added layer of accuracy and simplifies user management for the homeowner by providing images of each authorized user.<img src="https://images.wevolver.com/eyJidWNrZXQiOiJ3ZXZvbHZlci1wcm9qZWN0LWltYWdlcyIsImtleSI6ImZyb2FsYS8xNzI1ODUzMjcwNDY5LUZpZ3VyZTJfRGV0ZWN0aW9uX2F1dGhvcml6YXRpb25fcHJvY2Vzcy53ZWJwIiwiZWRpdHMiOnsicmVzaXplIjp7IndpZHRoIjo5NTAsImZpdCI6ImNvdmVyIn19fQ==" style="width: 100%px;" class="fr-fic fr-dib">Figure 2: The smart door lock’s detection and authorization process ensures accuracy while simplifying user management. (Source: AMD)This advanced smart door lock system also works in complete darkness and can recognize authorized people even while they are wearing glasses, hats, or facial covers.The AMD Zynq 7000 SoC design can be easily configured and customized by OEMs with help on hand from Makarena Labs, providing a lock that can store a family’s authorized faces and accurately authorize or reject them in under a second. For applications that need to store a larger number of faces, such as a neighborhood’s security gate, the higher performance AMD&nbsp;<a href="https://www.mouser.com/new/xilinx/xilinx-zynq-ultrascale-mpsocs/" target="_blank">Zynq UltraScale+™ MPSoC</a> can support fast recognition even with hundreds of authorized faces. Both parts include robust security engines, which OEM customers can configure to load only authentically signed, encrypted firmware.If you're interested in hearing more about the smart lock solution, please reach out to sales@makarenalabs.com.AMD, and the AMD Arrow logo, UltraScale+, Zynq, and combinations thereof are trademarks of Advanced Micro Devices, Inc.The <a href="https://community.amd.com/t5/adaptive-computing/smart-door-locks-enhancing-security-with-machine-learning/ba-p/583320" rel="noreferrer nofollow" target="_blank">Smart Door Locks – Enhancing Security with Machine Learning</a> blog was first published on amd.com and was reposted here with permission.<hr>Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies, from the endpoint to the edge to the cloud. Specializing in programmable logic devices, Xilinx is the semiconductor company that invented the Field Programmable Gate Array (FPGA), the hardware programmable System on Chip (SoC), and the Adaptive Compute Acceleration Platform (ACAP).

In this blog, we discuss how smart door technology is bringing peace of mind to the front door and more with a superior level of security.

Smart Door Locks - Enhancing Security with Machine Learning

Quantum computers, on the other hand, promise to rapidly crack complex cryptographic systems that a classical computer might never be able to unravel. This promise is based on a quantum factoring algorithm proposed in 1994 by&nbsp;<a href="https://news.mit.edu/2023/weird-weird-quantum-world-peter-shor-killian-lecture-0310" target="_blank">Peter Shor</a>, who is now a professor at MIT.But while researchers have taken great strides in the last 30 years, scientists have yet to build a quantum computer powerful enough to run Shor’s algorithm.As some researchers work to build larger quantum computers, others have been trying to improve Shor’s algorithm so it could run on a smaller quantum circuit. About a year ago, New York University computer scientist Oded Regev proposed a <a href="https://arxiv.org/pdf/2308.06572" target="_blank">major theoretical improvement</a>. His algorithm could run faster, but the circuit would require more memory.Building off those results, MIT researchers have proposed a best-of-both-worlds approach that combines the speed of Regev’s algorithm with the memory-efficiency of Shor’s. This new algorithm is as fast as Regev’s, requires fewer quantum building blocks known as qubits, and has a higher tolerance to quantum noise, which could make it more feasible to implement in practice.In the long run, this new algorithm could inform the development of novel encryption methods that can withstand the code-breaking power of quantum computers.“If large-scale quantum computers ever get built, then factoring is toast and we have to find something else to use for cryptography. But how real is this threat? Can we make quantum factoring practical? Our work could potentially bring us one step closer to a practical implementation,” says Vinod Vaikuntanathan, the Ford Foundation Professor of Engineering, a member of the Computer Science and Artificial Intelligence Laboratory (CSAIL), and senior author of a&nbsp;<a href="https://eprint.iacr.org/2023/1501.pdf" target="_blank" data-lf-fd-inspected-kn9eq4roawkarlvp="true">paper describing the algorithm</a>.The paper’s lead author is Seyoon Ragavan, a graduate student in the MIT Department of Electrical Engineering and Computer Science. The research will be presented at the 2024 International Cryptology Conference.<h2>Cracking cryptography</h2>To securely transmit messages over the internet, service providers like email clients and messaging apps typically rely on RSA, an <a href="https://people.csail.mit.edu/rivest/Rsapaper.pdf" target="_blank" data-lf-fd-inspected-kn9eq4roawkarlvp="true">encryption scheme</a> invented by MIT researchers Ron Rivest, Adi Shamir, and Leonard Adleman in the 1970s (hence the name “RSA”). The system is based on the idea that factoring a 2,048-bit integer (a number with 617 digits) is too hard for a computer to do in a reasonable amount of time.That idea was flipped on its head in 1994 when Shor, then working at Bell Labs, introduced an algorithm which proved that a quantum computer could factor quickly enough to break RSA cryptography.“That was a turning point. But in 1994, nobody knew how to build a large enough quantum computer. And we’re still pretty far from there. Some people wonder if they will ever be built,” says Vaikuntanathan.It is estimated that a quantum computer would need about&nbsp;<a href="https://quantum-journal.org/papers/q-2021-04-15-433/" target="_blank">20 million qubits</a> to run Shor’s algorithm. Right now, the largest quantum computers have around 1,100 qubits.A quantum computer performs computations using quantum circuits, just like a classical computer uses classical circuits. Each quantum circuit is composed of a series of operations known as quantum gates. These quantum gates utilize qubits, which are the smallest building blocks of a quantum computer, to perform calculations.But quantum gates introduce noise, so having fewer gates would improve a machine’s performance. Researchers have been striving to enhance Shor’s algorithm so it could be run on a smaller circuit with fewer quantum gates.That is precisely what Regev did with the circuit he proposed a year ago.“That was big news because it was the first real improvement to Shor’s circuit from 1994,” Vaikuntanathan says.The quantum circuit Shor proposed has a size proportional to the square of the number being factored. That means if one were to factor a 2,048-bit integer, the circuit would need millions of gates.Regev’s circuit requires significantly fewer quantum gates, but it needs many more qubits to provide enough memory. This presents a new problem.“In a sense, some types of qubits are like apples or oranges. If you keep them around, they decay over time. You want to minimize the number of qubits you need to keep around,” explains Vaikuntanathan.He heard Regev speak about his results at a workshop last August. At the end of his talk, Regev posed a question: Could someone improve his circuit so it needs fewer qubits? Vaikuntanathan and Ragavan took up that question.<h2>Quantum ping-pong</h2>To factor a very large number, a quantum circuit would need to run many times, performing operations that involve computing powers, like 2 to the power of 100.But computing such large powers is costly and difficult to perform on a quantum computer, since quantum computers can only perform reversible operations. Squaring a number is not a reversible operation, so each time a number is squared, more quantum memory must be added to compute the next square.The MIT researchers found a clever way to compute exponents using a series of <a href="https://en.wikipedia.org/wiki/Fibonacci_sequence" target="_blank">Fibonacci numbers</a> that requires simple multiplication, which is reversible, rather than squaring. Their method needs just two quantum memory units to compute any exponent.“It is kind of like a ping-pong game, where we start with a number and then bounce back and forth, multiplying between two quantum memory registers,” Vaikuntanathan adds.They also tackled the challenge of error correction. The circuits proposed by Shor and Regev require every quantum operation to be correct for their algorithm to work, Vaikuntanathan says. But error-free quantum gates would be infeasible on a real machine.They overcame this problem using a technique to filter out corrupt results and only process the right ones.The end-result is a circuit that is significantly more memory-efficient. Plus, their error correction technique would make the algorithm more practical to deploy.“The authors resolve the two most important bottlenecks in the earlier quantum factoring algorithm. Although still not immediately practical, their work brings quantum factoring algorithms closer to reality,” adds Regev.In the future, the researchers hope to make their algorithm even more efficient and, someday, use it to test factoring on a real quantum circuit.“The elephant-in-the-room question after this work is: Does it actually bring us closer to breaking RSA cryptography? That is not clear just yet; these improvements currently only kick in when the integers are much larger than 2,048 bits. Can we push this algorithm and make it more feasible than Shor’s even for 2,048-bit integers?” says Ragavan.

The most recent email you sent was likely encrypted using a tried-and-true method that relies on the idea that even the fastest computer would be unable to efficiently break a gigantic number into factors.

Toward a code-breaking quantum computer

Brain-machine interfaces (BMIs) have emerged as a promising solution for restoring communication and control to individuals with severe motor impairments. Traditionally, these systems have been bulky, power-intensive, and limited in their practical applications. Researchers at EPFL have developed the first high-performance, Miniaturized Brain-Machine Interface (MiBMI), offering an extremely small, low-power, highly accurate, and versatile solution. Published in <a href="https://ieeexplore.ieee.org/document/10643873" target="_blank" rel="noopener">the latest issue of the IEEE Journal of Solid-State Circuits</a> and presented at the International Solid-State Circuits Conference, the MiBMI not only enhances the efficiency and scalability of brain-machine interfaces but also paves the way for practical, fully implantable devices. This technology holds the potential to significantly improve the quality of life for patients with conditions such as amyotrophic lateral sclerosis (ALS) and spinal cord injuries.<blockquote>This advancement brings us closer to practical, implantable solutions.<footer>Mahsa Shoaran</footer></blockquote>The MiBMI's small size and low power are key features, making the system suitable for implantable applications. Its minimal invasiveness ensures safety and practicality for use in clinical and real-life settings. It is also a fully integrated system, meaning that the recording and processing are done on two extremely small chips with a total area of 8mm2. Thisis the latest in a new class of low-power BMI devices developed at Mahsa Shoaran’s Integrated Neurotechnologies Laboratory (<a href="https://www.epfl.ch/labs/inl/" target="_blank">INL</a>) at EPFL’s IEM and Neuro X institutes.<img src="https://images.wevolver.com/eyJidWNrZXQiOiJ3ZXZvbHZlci1wcm9qZWN0LWltYWdlcyIsImtleSI6ImZyb2FsYS8xNzI1NTgzMDExNzczLTI4ODE1MWE4LmpwZyIsImVkaXRzIjp7InJlc2l6ZSI6eyJ3aWR0aCI6OTUwLCJmaXQiOiJjb3ZlciJ9fX0=" style="width: 100%px;" class="fr-fic fr-dib">Miniaturized Brain-Machine Interface (MiBMI) - 2024 EPFL / Lundi13 - CC-BY-SA 4.0“MiBMI allows us to convert intricate neural activity into readable text with high accuracy and low power consumption. This advancement brings us closer to practical, implantable solutions that can significantly enhance communication abilities for individuals with severe motor impairments,” says Shoaran.<h3 skip="true">Brain-to-text conversion involves decoding neural signals generated when a person imagines writing letters or words. In this process, electrodes implanted in the brain record neural activity associated with the motor actions of handwriting. The MiBMI chipset then processes these signals in real-time, translating the brain’s intended hand movements into corresponding digital text. This technology allows individuals, especially those with locked-in syndrome and other severe motor impairments, to communicate by simply thinking about writing, with the interface converting their thoughts into readable text on a screen.</h3><blockquote id="isPasted">The chip converts handwriting activity into text with an impressive 91% accuracy.<footer>Mohammed Ali Shaeri</footer></blockquote>“While the chip has not yet been integrated into a working BMI, it has processed data from previous live recordings, such as those from the Shenoy lab at Stanford, converting handwriting activity into text with an impressive 91% accuracy,” says lead author Mohammed Ali Shaeri. The chip can currently decode up to 31 different characters, an achievement unmatched by any other integrated systems. “We are confident that we can decode up to 100 characters, but a handwriting dataset with more characters is not yet available,” adds Shaeri.Current BMIs record the data from electrodes implanted in the brain and then send these signals to a separate computer to do the decoding. The MiBMI chips records the data but also processes the information in real time—integrating a 192-channel neural recording system with a 512-channel neural decoder. This neurotechnological breakthrough is a feat of extreme miniaturization that combines expertise in integrated circuits, neural engineering, and artificial intelligence. This innovation is particularly exciting in the emerging era of neurotech startups in the BMI domain, where integration and miniaturization are key focuses. EPFL's MiBMI offers promising insights and potential for the future of the field.<blockquote>Our goal is to develop a versatile BMI that can be tailored to various neurological disorders, providing a broader range of solutions for patients.<footer>Mahsa Shoaran</footer></blockquote>To be able to process the massive amount of information picked up by the electrodes on the miniaturized BMI, the researchers had to take a completely different approach to data analysis. They discovered that the brain activity for each letter, when the patient imagines writing it by hand, contains very specific markers, which the researchers have named distinctive neural codes (DNCs). Instead of processing thousands of bytes of data for each letter, the microchip only needs to process the DNCs, which are around a hundred bytes. This makes the system fast, accurate, and with low-power consumption. This breakthrough also allows for faster training times, making learning how to use the BMI easier and more accessible.Collaborations with other teams at EPFL’s Neuro-X and IEM Institutes, such as with the laboratories of Grégoire Courtine, Silvestro Micera, Stéphanie Lacour, and David Atienza promise to create the next generation of integrated BMI systems. Shoaran, Shaeri and their team are exploring various applications for the MiBMI system beyond handwriting recognition. “We are collaborating with other research groups to test the system in different contexts, such as speech decoding and movement control. Our goal is to develop a versatile BMI that can be tailored to various neurological disorders, providing a broader range of solutions for patients,” says Shoaran.<hr>ReferencesM. A. Shaeri, U. Shin, A. Yadav, R. Caramellino, G. Rainer and M. Shoaran, "MiBMI: A 192/512-Channel 2.46mm² Miniaturized Brain-Machine Interface Chipset Enabling 31-Class Brain-to-Text Conversion Through Distinctive Neural Codes," 2024 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2024, pp. 546-548,&nbsp;<a href="https://ieeexplore.ieee.org/document/10643873/" target="_blank" rel="noopener">doi: 10.1109/ISSCC49657.2024.10454533</a>.M. A. Shaeri, U. Shin, A. Yadav, R. Caramellino, G. Rainer, M. Shoaran, “A 2.46mm2 Miniaturized Brain-Machine Interface (MiBMI) Enabling 31-Class Brain-to-Text Decoding”, in IEEE Journal of Solid-State Circuits (JSSC), 2024,&nbsp;<a href="https://ieeexplore.ieee.org/document/10643873" target="_blank" rel="noopener">doi: 10.1109/JSSC.2024.3443254</a>

Researchers from EPFL have developed a next-generation miniaturized brain-machine interface - 2024 EPFL / Lundi13 - CC-BY-SA 4.0

Researchers from EPFL have developed a next-generation miniaturized brain-machine interface capable of direct brain-to-text communication on tiny silicon chips.

An entire brain-machine interface on a chip

A view into how nanoscale building blocks can rearrange into different organized structures on command is now possible with an approach that combines an electron microscope, a small sample holder with microscopic channels, and computer simulations, according to a new study by researchers at the University of Michigan and Indiana University.The approach could eventually enable smart materials and coatings that can switch between different optical, mechanical and electronic properties.“One of my favorite examples of this phenomenon in nature is in chameleons,” said <a href="https://che.engin.umich.edu/people/dwyer-tobias/" target="_blank" rel="noreferrer noopener">Tobias Dwyer</a>, U-M doctoral student in chemical engineering and co-first author of the study published in Nature Chemical Engineering. “Chameleons change color by altering the spacing between nanocrystals in their skin. The dream is to design a dynamic and multifunctional system that can be as good as some of the examples that we see in biology.”The imaging technique lets researchers watch how nanoparticles react to changes in their environment in real time, offering an unprecedented window into their assembly behavior.<img src="https://images.wevolver.com/eyJidWNrZXQiOiJ3ZXZvbHZlci1wcm9qZWN0LWltYWdlcyIsImtleSI6ImZyb2FsYS8xNzI1MzIxMzE4NjkzLWZsb3ctY2VsbC5qcGciLCJlZGl0cyI6eyJyZXNpemUiOnsid2lkdGgiOjk1MCwiZml0IjoiY292ZXIifX19" style="width: 100%px;" class="fr-fic fr-dib">An illustration of an imaging technique that allows researchers to watch how nanoparticles respond to changes in their environment in real time. The blue lines represent the beam of an electron microscope as it impacts gold nanoblocks suspended in liquid in a small sample holder device called a liquid flow cell. Image credit: Ella Maru Studio.In the study, the Indiana team first suspended nanoparticles, a class of materials smaller than the average bacteria cell, in tiny channels of liquid on a microfluidic flow cell. This type of device allowed the researchers to flush different kinds of fluid into the cell on the fly while they viewed the mixture under their electron microscope. The researchers learned that the instrument gave the nanoparticles—which normally are attracted to each other—just enough electrostatic repulsion to push them apart and allow them to assemble into ordered arrangements.The nanoparticles, which are cubes made of gold, either perfectly aligned their faces in a tidy cluster or formed a more messy arrangement. The final arrangement of the material depended on the properties of the liquid the blocks were suspended in, and flushing new liquids into the flow cell caused the nanoblocks to switch between the two arrangements.The experiment was a proof of concept for how to steer nanoparticles into desired structures. Nanoparticles are too small to manually manipulate, but the approach could help engineers learn to reconfigure other nanoparticles by changing their environment.“You might have been able to move the particles into new liquids before, but you wouldn’t have been able to watch how they respond to their new environment in real-time,” said <a href="https://www.chem.indiana.edu/faculty/xingchen-ye/" target="_blank">Xingchen Ye</a>, IU associate professor of chemistry who developed the experimental technique and is the study’s lead corresponding author.“We can use this tool to image many types of nanoscale objects, like chains of molecules, viruses, lipids and composite particles. Pharmaceutical companies could use this technique to learn how viruses interact with cells in different conditions, which could impact drug development.”<img src="https://s3-us-west-1.amazonaws.com/wevolver-project-images/froala%2F1725321753505-ezgif-6-b9c5db5d11.gif" style="width: 100%px;" class="fr-fic fr-dib">A view through an electron microscope of gold nanoparticles reconfiguring themselves in response to researchers changing the liquid the gold nanoparticles are suspended in—either butanol or a mix of octane and butanol. The black and white image on the left is unedited. At right, the gold nanoparticles are color-coded by their orientation. Initially floating in butanol, they’re arranged in a skewed crystal with more unfilled space in its center. Green and orange particles are mixed with blue particles. After researchers change the liquid to a mixture of butanol and octane, the squares’ faces align more closely together and more of the squares in the center of the crystal turn blue and green, representing a more ordered arrangement. Animation credit: Tobias Dwyer, Glotzer Lab, University of Michigan.An electron microscope isn’t necessary to activate the particles in practical morphable materials, the researchers said. Changes in light and pH could also serve that purpose.But to extend the technique to different kinds of nanoparticles, the researchers will need to know how to change their liquids and microscope settings to arrange the particles. Computer simulations run by the U-M team open the door to that future work by identifying the forces that caused the particles to interact and assemble.“We think we now have a good enough understanding of all the physics at play to predict what would happen if we use particles of a different shape or material,” said&nbsp;<a href="https://che.engin.umich.edu/people/moore-timothy/" target="_blank" rel="noreferrer noopener">Tim Moore</a>, U-M assistant research scientist of chemical engineering and co-first author of the study. He designed the computer simulations together with Dwyer and&nbsp;<a href="https://che.engin.umich.edu/people/glotzer-sharon/" target="_blank" rel="noreferrer noopener">Sharon Glotzer</a>, the Anthony C. Lembke Department Chair of Chemical Engineering at U-M and a corresponding author of the study.“The combination of experiments and simulations is exciting because we now have a platform to design, predict, make and observe in real time new, morphable materials together with our IU partners,” said Glotzer, who is also the John Werner Cahn Distinguished University Professor and Stuart W. Churchill Collegiate Professor of Chemical Engineering.

It’s a step toward smart coatings that change color—or other properties—on the fly.

Morphable materials: Researchers coax nanoparticles to reconfigure themselves

The emergence of Artificial Intelligence (AI) and Machine Learning (ML) is one of the most significant computing trends in recent history. According to research, by 2027, spending on AI software alone will grow to nearly $300B, with a CAGR of 19.1% [1]. And, as the software half of the AI/ML world is growing at meteoric rates, the hardware side is also teeming with innovation. Similar research suggests that the AI accelerator market will increase from $21B in 2024 to $33B by 2028 [2].AI/ML is a software-driven pursuit and can have very different requirements depending on the market and application (i.e., automotive, IoT, cloud, training vs inference, etc). Supporting this fast moving and diverse software market requires a collaborative,industry-wide effort to develop flexible and customized domain-specific hardware solutions optimized for this range of AI workloads. Innovation means that the market should not be limited to a few key players. Rather, the process needs to be democratized to enable everyone, enterprises and startups, to contribute their ideas to the growing AI/ML computing landscape.&nbsp;RISC-V has become a preferred standard for designing the industry’s most performant and efficient AI/ML computing resources. Let’s take a look at what’s happening in the world of RISC-V for AI/ML and discover why RISC-V is a key technology for supporting the industry’s future.&nbsp;<h1 dir="ltr">Why RISC-V for AI/ML?</h1>RISC-V is a compelling architecture for the development of AI/ML systems.The extensible industry standard RISC-V ISA enables a software-focused approach to AI hardware, freeing developers from the restrictions of proprietary compute. RISC-V provides a common language for AI development, as an industry standard ISA, creating a cohesive ecosystem for AI/ML development. This robust and highly capable ecosystem of member companies, organizations, technologists, enthusiasts and academics, brings the expertise and technologies that can deliver future generations of innovative new AI systems.<h2 dir="ltr">Software-Focused Hardware</h2>RISC-V introduces new paradigms to the world of hardware design by enabling the concept of software-focused hardware. AI/ML is software defined, built on frameworks such as TensorFlow, ONNX and OneAPI, and rapidly evolving algorithms. Transformers, the basis of the recent boom in AI were <a href="https://research.google/pubs/attention-is-all-you-need/" target="_blank">only introduced in 2017</a>. New algorithms will emerge, requiring new hardware to run on, and while it is not possible to predict these algorithms, by using RISC-V we can prepare to support them with optimized hardware delivered fast.&nbsp;Historically, software designers have been constrained by the restrictions of proprietary hardware platforms. The development process involved designing applications to the constraints of predefined hardware, ultimately limiting performance and efficiency. Not every AI/ML workload belongs on a GPU. Instead of developing software to fit the constraints of predefined hardware, RISC-V’s modular architecture enables industry leading differentiation, through the development of custom processors and accelerators developed precisely for the requirements of specific AI workloads such as energy efficient IoT and powerful HPC applications.&nbsp;The configurability and openness of RISC-V enables a “software-focused” design paradigm, wherein hardware customization for specific workloads becomes feasible without the constraints imposed by proprietary instruction sets. This is achieved through RISC-V’s modular architecture, which allows developers to define custom extensions and instructions tailored to their unique workloads. For example, in AI/ML applications, developers can implement specialized instructions for matrix multiplications and vector processing—key operations in neural network computations.Using custom instructions, such as Single Instruction, Multiple Data (SIMD) operations, RISC-V processors can execute multiple data points with a single instruction, significantly boosting performance in parallel processing tasks common in AI/ML workloads. Additionally, hardware accelerators tailored to AI tasks can be integrated seamlessly. These accelerators, including tensor processing units (TPUs) or specialized neural processing units (NPUs), are designed to handle the intensive mathematical operations required for deep learning models, such as convolutions and backpropagation.This high degree of customization leads to superior computational efficiency, as the processor is optimized for specific tasks rather than relying on a generic, one-size-fits-all solution. Moreover, RISC-V’s ability to support fine-grained power management techniques reduces power consumption. For instance, designers can implement dynamic voltage and frequency scaling (DVFS) tailored to the specific needs of AI/ML tasks, reducing power usage without compromising performance.Furthermore, the RISC-V standard promotes rapid innovation and cost-effective development. Developers can contribute to and benefit from a global ecosystem of shared knowledge and resources, facilitating rapid innovation and ultimately a faster time-to-market. This collective effort ensures that the latest advancements in AI/ML can be quickly integrated into hardware designs, keeping pace with the fast-evolving demands of the field.<h2 dir="ltr">Creating a Common Language</h2>The RISC-V instruction set architecture (ISA) provides a uniform language for hardware and software developers, creating a cohesive ecosystem for AI/ML development. It allows developers to create tailored domain specific solutions with greater flexibility. Importantly, the controlled way in which this is enabled ensures that the base foundational software elements, such as those running on Linux, remain consistent and interoperable across different RISC-V implementations.Ultimately, RISC-V's unique proposition lies in its ability to foster AI/ML by leading the industry in providing the opportunity to build customized and differentiated solutions from standard and non-standard extensions. This enables domain-specific acceleration while maintaining the productivity benefits of a single, coherent programming model. RISC-V defines a small base feature set for implementers to use along with ratified extensions which they can use as required. Inside a single RISC-V based AI/ML SoC you can deeply customize different RISC-V cores for different jobs such as SoC Control or matrix multiplication, with these different cores all based on the same ISA, making them easier to program.&nbsp;To add to this flexibility, RISC-V permits the addition of vendor-specific extensions to differentiate products with application-specific functionality. RISC-V provides guidance and branding to implementors for interoperability requirements in market segments through the definition of “RISC-V Profiles"Offering a standardized yet flexible platform allows designers to rapidly integrate cutting-edge research into hardware without being hampered by proprietary constraints. Developers can leverage community contributions, such as optimized libraries and toolchains, to expedite the development process and enhance the performance of their AI/ML solutions.Beyond this, the RISC-V ISA presents a significant advantage in providing standardized, modular building blocks for various computing applications. This standardization enables hardware designers to develop and integrate components more seamlessly, reducing the complexity and cost typically associated with custom designs.By making custom designs more accessible, RISC-V makes an easier business case for the creation of optimized platforms for specific use cases, rather than compromise on having to use more generic hardware and software created for other high volume markets.&nbsp;<h2 dir="ltr" id="isPasted">A Highly Capable Ecosystem Delivering AI/ML Solutions on RISC-V </h2>The capabilities of the RISC-V member ecosystem enables AI developers to deliver the innovative software focused AI systems. From processor IP to design services and simulation to software components, the collective knowledge of these companies and organizations covers all the capabilities required to create custom software-focused AI/ML processing, enabling developers to concentrate on their innovation. The range of choice from this healthy market of ecosystem members prevents vendor lock-in and mitigates some of the supply chain challenges faced by other architectures. Alongside the capability to create custom processing, the RISC-V ecosystem also offers a range of pre-designed AI silicon, designed for different workloads.There’s no doubt that this RISC-V ecosystem has taken a foothold in the industry at large. In fact, so far, we estimate that more than 10 billion RISC-V processor cores have shipped [3]. Now, we’re seeing similar adoption in the AI/ML hardware markets, where reports are indicating that RISC-V-based AI SoCs will have a CAGR for units of 73.6% by 2027, while AI SoC unit shipments are projected to reach 25B by then. [4]. RISC-V is quickly becoming the defacto standard for building AI accelerators.&nbsp;Here are some of the highlights of RISC-V’s use in AI/ML.<ul><li dir="ltr">Meta’s MTIA v1 AI Inference Accelerator [5]</li><li dir="ltr">Esperanto ET-SoC-1 [6]</li><li dir="ltr">Google’s TPU [7]</li><li dir="ltr">SiFive Intelligence X390 [8]</li><li dir="ltr">StreamComputing STPC920 [10]</li><li dir="ltr">Ventana Veyron V2 [11]</li><li dir="ltr">Andes Technology QiLai SoC [12]</li><li dir="ltr">Semidynamics ‘All-In-One AI’ IP [13]</li><li dir="ltr">Axelera AI Metis AI Platform [14]</li><li dir="ltr">Project Open Se Cura [15]</li><li dir="ltr">Codeplay oneAPI Construction Kit [16]</li></ul><h1 dir="ltr">Conclusion</h1>As the AI/ML market continues to grow exponentially, RISC-V is poised to be a formidable driver of innovation and change for all. By offering a modular, open, and customizable architecture, RISC-V gives designers the creativity, power, and speed of innovation needed to address the diverse and evolving needs of AI/ML applications. Developers are empowered with the flexibility to tailor solutions to specific requirements while working in a unified and interoperable ecosystem. Finally, the community-driven innovation model of RISC-V accelerates the development of cutting-edge technologies and democratizes access to advanced hardware design for all.For more information on how RISC-V is driving the future of AI, visit <a href="http://www.riscv.org/ai" target="_blank">www.riscv.org/ai.</a><h1 dir="ltr">References</h1>[1]<a href="https://www.gartner.com/en/documents/4925331#:~:text=Summary,2023%20to%2035%25%20by%202027" target="_blank">https://www.gartner.com/en/documents/4925331#:~:text=Summary,2023%20to%2035%25%20by%202027</a>.[2] <a href="https://www.gartner.com/en/newsroom/press-releases/2024-05-29-gartner-forecasts-worldwide-artificial-intelligence-chips-revenue-to-grow-33-percent-in-2024#:~:text=Gartner%20forecasts%20AI%20PC%20shipments,will%20be%20an%20AI%20PC" target="_blank" rel="noopener noreferrer">https://www.gartner.com/en/newsroom/press-releases/2024-05-29-gartner-forecasts-worldwide-artificial-intelligence-chips-revenue-to-grow-33-percent-in-2024#:~:text=Gartner%20forecasts%20AI%20PC%20shipments,will%20be%20an%20AI%20PC</a>.[3]<a href="https://riscv.org/news/2022/07/europe-steps-up-as-risc-v-ships-10bn-cores-nick-flaherty-ee-news-europe/" target="_blank">https://riscv.org/news/2022/07/europe-steps-up-as-risc-v-ships-10bn-cores-nick-flaherty-ee-news-europe/</a>[4] <a href="https://semico.com/content/analyzing-risc-v-cpu-market-sip-socs-ai-and-design-starts" target="_blank" rel="noopener noreferrer">https://semico.com/content/analyzing-risc-v-cpu-market-sip-socs-ai-and-design-starts</a>[5]<a href="https://ai.meta.com/blog/meta-training-inference-accelerator-AI-MTIA/" target="_blank">https://ai.meta.com/blog/meta-training-inference-accelerator-AI-MTIA/</a>[6]<a href="https://www.esperanto.ai/products/" target="_blank">https://www.esperanto.ai/products/</a>[7] <a href="https://riscv.org/wp-content/uploads/2018/12/Antmicro-RISC-V-Summit-Keynote.pdf" target="_blank" data-lf-fd-inspected-kn9eq4roawkarlvp="true">https://riscv.org/wp-content/uploads/2018/12/Antmicro-RISC-V-Summit-Keynote.pdf</a>[8] <a href="https://www.sifive.com/cores/intelligence-x390" target="_blank">https://www.sifive.com/cores/intelligence-x390</a>[9] <a href="https://tenstorrent.com/hardware/wormhole" target="_blank">https://tenstorrent.com/hardware/wormhole</a>&nbsp;[10] <a href="https://www.streamcomputing.com/en/index.php?s=product&c=category&id=2" target="_blank">https://www.streamcomputing.com/en/index.php?s=product&amp;c=category&amp;id=2</a>[11] <a href="https://www.ventanamicro.com/ventana-introduces-veyron-v2/" target="_blank">https://www.ventanamicro.com/ventana-introduces-veyron-v2/</a>[12] <a href="https://www.andestech.com/en/2024/05/30/andes-technology-announced-the-qilai-soc-and/" target="_blank">https://www.andestech.com/en/2024/05/30/andes-technology-announced-the-qilai-soc-and/</a>[13] <a href="https://semidynamics.com/en/resources/press-releases" target="_blank">https://semidynamics.com/en/resources/press-releases</a>[14] <a href="https://www.axelera.ai/blog/the-metis-ai-platform-in-detail" target="_blank">https://www.axelera.ai/blog/the-metis-ai-platform-in-detail</a>[15] <a href="https://opensource.googleblog.com/2023/11/project-open-se-cura-open-source-announcement.html" target="_blank">https://opensource.googleblog.com/2023/11/project-open-se-cura-open-source-announcement.html</a>[16] <a href="https://developer.codeplay.com/products/oneapi/construction-kit/home/" target="_blank" rel="noopener noreferrer">https://developer.codeplay.com/products/oneapi/construction-kit/home/</a>

RISC-V: introducing new paradigms to the world of hardware design with software-focused hardware.

RISC-V Enables Performant and Flexible AI and ML Compute

On a research cruise around Hawaii in 2018, Yuening Zhang SM ’19, PhD ’24 saw how difficult it was to keep a tight ship. The careful coordination required to map underwater terrain could sometimes led to a stressful environment for team members, who might have different understandings of which tasks must be completed in spontaneously changing conditions. During these trips, Zhang considered how a robotic companion could have helped her and her crewmates achieve their goals more efficiently. Six years later, as a research assistant in the MIT Computer Science and Artificial Intelligence Laboratory (CSAIL), Zhang developed what could be considered a missing piece: an AI assistant that communicates with team members to align roles and accomplish a common goal. In a paper presented at the International Conference on Robotics and Automation (ICRA) and&nbsp;<a href="https://ieeexplore.ieee.org/document/10609865" target="_blank">published on IEEE Xplore on Aug. 8</a>, she and her colleagues present a system that can oversee a team of both human and AI agents, intervening when needed to potentially increase teamwork effectiveness in domains like search-and-rescue missions, medical procedures, and strategy video games. The CSAIL-led group has developed a theory of mind model for AI agents, which represents how humans think and understand each other’s possible plan of action when they cooperate in a task. By observing the actions of its fellow agents, this new team coordinator can infer their plans and their understanding of each other from a prior set of beliefs. When their plans are incompatible, the AI helper intervenes by aligning their beliefs about each other, instructing their actions, as well as asking questions when needed. For example, when a team of rescue workers is out in the field to triage victims, they must make decisions based on their beliefs about each other’s roles and progress. This type of epistemic planning could be improved by CSAIL’s software, which can send messages about what each agent intends to do or has done to ensure task completion and avoid duplicate efforts. In this instance, the AI helper may intervene to communicate that an agent has already proceeded to a certain room, or that none of the agents are covering a certain area with potential victims. “Our work takes into account the sentiment that ‘I believe that you believe what someone else believes,’” says Zhang, who is now a research scientist at Mobi Systems. “Imagine you’re working on a team and you ask yourself, ‘What exactly is that person doing? What am I going to do? Does he know what I am about to do?’ We model how different team members understand the overarching plan and communicate what they need to accomplish to help complete their team’s overall goal.” AI to the rescue Even with a sophisticated plan, both human and robotic agents will encounter confusion and even make mistakes if their roles are unclear. This plight looms especially large in search-and-rescue missions, where the objective may be to locate someone in danger despite limited time and a vast area to scan. Thankfully, communication technology augmented with the new robotic assistant could potentially notify the search parties about what each group is doing and where they’re looking. In turn, the agents could navigate their terrain more efficiently.This type of task organization could aid in other high-stakes scenarios like surgeries. In these cases, the nurse first needs to bring the patient to the operation room, then the anesthesiologist puts the patient to sleep before the surgeons begin the operation. Throughout the operation, the team must continuously monitor the patient’s condition while dynamically responding to the actions of each colleague. To ensure that each activity within the procedure remains well-organized, the AI team coordinator could oversee and intervene if confusion about any of these tasks arises.Effective teamwork is also integral to video games like “Valorant,” where players collaboratively coordinate who needs to attack and defend against another team online. In these scenarios, an AI assistant could pop up on the screen to alert individual users about where they’ve misinterpreted which tasks they need to complete.Before she led the development of this model, Zhang designed EPike, a computational model that can act as a team member. In a 3D simulation program, this algorithm controlled a robotic agent that needed to match a container to the drink chosen by the human. As rational and sophisticated as they may be, cases arise where these AI-simulated bots are limited by their misconceptions about their human partners or the task. The new AI coordinator can correct the agents’ beliefs when needed to resolve potential problems, and it consistently intervened in this instance. The system sent messages to the robot about the human’s true intentions to ensure it matched the container correctly.“In our work on human-robot collaboration, we’ve been both humbled and inspired over the years by how fluid human partners can be,” says Brian C. Williams, MIT professor of aeronautics and astronautics, CSAIL member, and senior author on the study. “Just look at a young couple with kids, who work together to get their kids breakfast and off to school. If one parent sees their partner serving breakfast and still in their bathrobe, the parent knows to shower quickly and shuffle the kids off to school, without the need to say a word. Good partners are well in tune with the beliefs and goals of each other, and our work on epistemic planning strives to capture this style of reasoning.”The researchers' method incorporates probabilistic reasoning with recursive mental modeling of the agents, allowing the AI assistant to make risk-bounded decisions. In addition, they focused on modeling agents’ understanding of plans and actions, which could complement previous work on modeling beliefs about the current world or environment. The AI assistant currently infers agents’ beliefs based on a given prior of possible beliefs, but the MIT group envisions applying machine learning techniques to generate new hypotheses on the fly. To apply this counterpart to real-life tasks, they also aim to consider richer plan representations in their work and reduce computation costs further.Dynamic Object Language Labs President Paul Robertson, Johns Hopkins University Assistant Professor Tianmin Shu, and former CSAIL affiliate Sungkweon Hong PhD ’23 join Zhang and Williams on the paper. Their work was supported, in part, by the U.S. Defense Advanced Research Projects Agency (DARPA) Artificial Social Intelligence for Successful Teams (ASIST) program.

A system developed by MIT CSAIL researchers can oversee a team of both human and AI agents, communicating with team members to align roles and accomplish a common goal. Image: Alex Shipps/MIT CSAIL

An AI team coordinator aligns agents’ beliefs about how to achieve a task, intervening when necessary to potentially help with tasks in search and rescue, hospitals, and video games.

AI assistant monitors teamwork to promote effective collaboration

Automatic speech recognition and translation systems such as the Lecture Translator of the Karlsruhe Institute of Technology (KIT) can convert the spoken word in lectures into a text in several languages in real time. Such systems improve access to information for students with disabilities and foreign students. They also speed up work and learning in general through intelligent post-processing and archiving of spoken texts. KIT researchers have added new functions to the Lecture Translator. Automatic recognition of the spoken word in several languages at the same time, text segmentation and title generation in real time, summaries and links to technical terms as well as queries on what has been heard now make it easier to understand and efficiently process lectures."With Lecture Translator's automatic simultaneous translation, we have brought spoken lectures closer to an international audience. However, this usually represents only 15 percent of the audience. With the new AI tools, we want to break down not only language barriers, but also comprehension barriers," says Alexander Waibel, Professor of Computer Science at KIT. "Automatically transcribed texts of spoken language are often difficult to read, because they appear too quickly as a long text without paragraphs and subheadings - just as the lecture was delivered orally". Processing the lecture is also time-consuming, because you have to search the lecture for gaps in understanding," says Waibel.<h2>Better overview of documents</h2>The further development of the Lecture Translator provides a remedy. The researchers have developed several new automatic functions such as "Smart Chaptering", "Summarization", "Q&amp;A" and "Auto-Links". A new type of artificial intelligence (AI) that automatically recognizes language converts the spoken text into a transcript in multiple languages and automatically identifies paragraphs, chapter headings and key points. It also creates an acoustic rendition in which the user can select one of 18 languages. The program also automatically displays links as cross-references to relevant sources in lecture notes or Wikipedia, which students can use to better process the lecture. "With our new AI models, conversations and lectures can be better structured and even videos can be divided into easily navigable chapters," says Waibel. This enables better understanding not only during the lecture, but also after the lecture.<h2>Lecture Translator translates into 18 languages</h2>The research team has integrated the work into the Lecture Translator, which is used at KIT to automatically transcribe lectures in real time. Chapter division, title generation, paragraph layout, summaries with links - which can also be used online and offline - now extend the Lecture Translator service and make it easier to work with the material. Translation is available in 18 languages. The technology has specific applications for content creators, students, teachers and podcasters who can structure their audio and video content for the first time. "Users can navigate through videos and lectures more efficiently, find relevant sections more quickly, and capture important core content more compactly and efficiently - they have a much better overall view and faster access to details," says Waibel.The research was carried out as part of the project "How is AI Changing Science?" and was funded for four years by the Volkswagen Foundation. In addition to KIT, the University of Bonn and the University of Vienna were also involved in the project.<a href="https://www.kcist.kit.edu/" target="_blank">Details on the KIT Center Information - Systems - Technologies</a>

With new functions such as automatic chapter division and summaries, the Lecture Translator offers improved speech recognition. (Photo: Markus Breig, KIT)

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