The semiconductor industry is increasingly adopting a chiplet-based architecture as a practical solution to the growing complexities, costs, and scalability challenges associated with traditional monolithic integrated circuits.With the increasing price of advanced process nodes and longer design cycles, semiconductor companies are investigating new options for delivering higher performance, more flexibility, and faster product development. One of the most successful solutions has been the rise of chiplet technology, empowering complex systems to be built from multiple specialized dies in a single package.The critical enabler for this design shift is efficient communication between individual chiplets. High-performance/low-power die-to-die interconnects are essential to make a multi-chip package operate as a single system, not a set of separate components.This need has led to the advent of Universal Chiplet Interconnect Express (UCIe), an open industry standard that ensures high-bandwidth, low-latency, low-power communication between chiplets. <a href="https://forwardedgeasic.com/ucie-ip/">FEASIC’s UCIe IP solution</a> fulfills this need with a full implementation of the UCIe-SP standard package architecture, permitting developers to accelerate the deployment of interoperable chiplet-based systems.<h2>Chiplet Architectures on the Rise</h2>For decades, semiconductor innovation meant putting more functionality on a single die. This has resulted in large performance gains but has likewise become increasingly complex to maintain. Manufacturing large monolithic chips is also difficult and can result in low yield, high fabrication cost, long development time, and high design complexity.Chiplet architecture provides a fundamentally different approach. Instead of building a single large die, engineers can split a system into smaller functional dies. Each of them can then be tuned for a particular job. Processor cores, AI accelerators, memory controllers, networking interfaces, and analog functions can be developed independently and then integrated into a common package.There are several advantages to this modular design philosophy. Smaller dies generally improve yields and reduce overall costs of production. Individual chiplets can also be reused across multiple products, which shortens development timelines and improves return on investment. Moreover, designers can combine technologies fabricated with different process nodes, so that each function can be realized with the most appropriate manufacturing technology. Each chiplet is allowed to progress at its own desired pace, which allows upgrading specific or critical parts of the design independently. The overall packaged product can then improve incrementally at a much lower cost.But the success of this approach depends on how well these chiplets can communicate with each other. Without a common communication framework, chiplet ecosystems are at risk of fragmenting due to proprietary interfaces and limited interoperability.This modular approach is also reshaping the broader chiplet ecosystem. Reusable components can now be developed once and integrated across multiple platforms, echoing how standardization and modular design transformed other segments of the technology industry.Rather than designing and fabricating every subsystem in-house, companies can source specialized chiplets from different suppliers and integrate them into application-specific solutions, fostering innovation, reducing development costs, and speeding up product launches. UCIe addresses these problems directly, offering a standardized foundation for chiplet interoperability.<img src="https://s3-us-west-1.amazonaws.com/wevolver-project-images/froala%2F1785253943231-1785253943230.jpeg" width="602" height="339" class="fr-fic fr-dii" />Engineers collaborating on a manufacturing project. Source: AdobeStock.<h2>UCIe: The Foundation for Chiplet Interoperability</h2>UCIe was created to address the interoperability issue that comes with chiplet adoption. The standard establishes a common die-to-die communication framework that allows chiplets from different vendors, foundries, and process technologies to cooperate in the same package.UCIe defines standardized physical, protocol, and software interfaces that eliminate many of the barriers that have traditionally made heterogeneous integration difficult. Instead of being forced to develop custom interconnects for each design, semiconductor designers can now leverage a common ecosystem supported by multiple industry players.This is particularly true for emerging applications that must move massive amounts of data between compute, memory, and accelerator resources. Efficient communication between multiple functional blocks is a key requirement for artificial intelligence workloads, high-performance computing systems, data center processors, and advanced edge-computing platforms. UCIe allows such systems to achieve high bandwidth density with low latency and power consumption.UCIe extends proven high-speed interconnect design principles to the package level, easing integration and allowing existing design methodologies to carry over to chiplet-based systems.<h2>FEASIC UCIe IP Solution</h2><a href="https://forwardedgeasic.com/">ForwardEdgeASIC (FEASIC)</a> has built a complete UCIe IP implementation that offers the basic infrastructure required for standards-compliant die-to-die communications. Instead of just offering individual building blocks, the company offers the complete UCIe stack, including the physical layer (PHY), die-to-die adapter functionality, and protocol support.This off-the-shelf solution enables customers to incorporate UCIe connectivity into their designs without the huge effort required to engineer a custom interconnect architecture. With a pre-validated solution, development teams can innovate on features specific to the application, while lowering the risk associated with implementations.The physical layer has been designed on the GlobalFoundries 12LP+ process technology and tuned for performance and power efficiency. FEASIC implementation supports x16 connectivity and provides transfer rates of up to 16 GT/s per lane to meet the high aggregate bandwidth required by today’s data-intensive applications.A key differentiator is that the solution has already been validated in the laboratory. And as the chiplet ecosystem matures, proven implementations gain value, as they reduce uncertainty in system integration and shorten qualification timelines.<img src="https://s3-us-west-1.amazonaws.com/wevolver-project-images/froala%2F1785253943239-1785253943239.jpeg" width="602" height="339" class="fr-fic fr-dii" />Futuristic cloud computing and edge-processing technologies. Source: AdobeStock.<h2>Future Outlook</h2>One of the biggest trends in modern chip design has been the move from monolithic semiconductor devices to modular chiplet architecture. As demand increases for artificial intelligence, machine learning, cloud computing, networking, and edge-processing applications, the ability to efficiently integrate multiple specialized dies in a single package will become increasingly important.UCIe provides the standardized foundation to turn this vision into reality. The standard enables high-speed, low-latency communication between chiplets, permitting developers to realize the full benefits of modular semiconductor design.FEASIC’s UCIe IP solution is a practical implementation of this technology, offering designers a validated and ready-to-deploy interconnect platform. It supports high-bandwidth communication, heterogeneous integration, and scalable multi-die architectures to help accelerate the industry’s transition to a more flexible and interoperable chiplet ecosystem.With semiconductor complexity continuing to grow, standardized die-to-die connectivity will be critical to the success of future generations of computing platforms. Solutions like FEASIC’s UCIe IP are helping to transition chiplets from an emerging concept to a core technology for next-generation semiconductor innovation.

The ForwardEdge ASIC (FEASIC) UCIe IP advances  the deployment of interoperable chiplet-based systems.

Accelerating the Adoption of Chiplet-Based Semiconductor Architectures

Europe and other regions have begun sunsetting 2G networks, and large-scale IoT deployments need a replacement connectivity solution before 2G goes dark. But replacing  2G fallback is not as simple as swapping in LTE-M (LTE for Machines) or NB-IoT (Narrowband IoT) with NTN (Non-Terrestrial Network) satellite fallback, because those standards don’t work for all applications and use cases. Cat 1 bis is a 4G standard that sits squarely between narrowband IoT and full LTE options. With a single-antenna design, global availability, and lower cost than original Cat 1, Cat 1 bis is a powerful solution to replace legacy 2G fallback solutions used today. Fortunately, Nordic Semiconductor offers a Cat 1 bis platform that can take engineers from simple evaluation all the way through to a certified product.<h2>2G Devices Are Leaving A Gap</h2>When most IoT devices are designed for field lifetimes of 10 years or longer, obsolete connectivity or lack of supplier support can be a threat to service life. Unfortunately, upgrading to a new network is not as simple as flashing new firmware to the board. Instead, designers need new cellular hardware, new certifications, and a connectivity roadmap that holds up for the next decade.The two most common replacements for 2G are LTE-M and NB-IoT, but both standards are meant for low-power, low-data-rate IoT applications. While many networks exist globally, LTE-M or NB-IoT are not currently available in all markets with 2G solutions. LTE-M tops out at 1 Mbps downlink, and NB-IoT has even less bandwidth, trading data rate for range and deeper indoor penetration. While many sensor or metering applications can work within those constraints, more sophisticated asset trackers or security cameras, for example, may need sustained multi-megabit throughput that exceeds those specifications. When application requirements outgrow LTE-M or NB-IoT, engineers have fewer options.One alternative is LTE Cat 1. While the original standard delivered up to 10 Mbps over existing 4G infrastructure, it required dual-antenna MIMO (Multiple-Input Multiple-Output), which added complexity and costs that rendered it impractical for IoT deployments. Additionally, Cat 1 and higher LTE categories are optimized for downlink-centric use cases versus the typical uplink-centric data flow needed in most IoT deployments. As a result, IoT engineers often face a trade-off between too little bandwidth or too much hardware.<h2>Cat 1 bis Offers a Better Option </h2>One powerful option for designers is Cat 1 bis, a 3GPP (3rd Generation Partnership Project) amendment to the original LTE Cat 1 standard. By dropping the MIMO requirement, Cat 1 bis unlocks single-antenna designs that reduce module size and bill of materials (BOM) costs compared to the original. And, with up to 10 Mbps downlink and 5 Mbps uplink rates, that reduced footprint still provides enough headroom for video streaming and responsive data exchange. Another meaningful benefit of Cat 1 bis is its compatibility with existing global 4G infrastructure. As a result, engineers can leverage the standard to build a single hardware configuration that supports global deployment rather than maintaining separate regional variants for different network environments.Even so, Cat 1 bis does not suit every application. For example, Cat 1 bis draws higher peak power than LTE-M and NB-IoT due to its inherent full-duplex radio configuration and complexity. Standards bodies and mobile network operators have also extended LTE-M and NB-IoT with NTN satellite options that extend beyond traditional terrestrial network footprints, providing those standards with better coverage in remote areas also as part of 5G. Where deep indoor coverage or sub-1 Mbps data rates are sufficient, LTE-M or NB-IoT may deliver adequate performance at lower power consumption. But, for applications that genuinely require multi-megabit throughput, global 4G availability, and a compact single-antenna form factor, Cat 1 bis fills a gap that narrowband standards simply can’t match.<h2>Nordic Semiconductor's Cat 1 bis Platform</h2>To support Cat 1 bis deployments, Nordic Semiconductor offers its nRF93M1 Smart Modem module. A dedicated Cat 1 bis solution, the module simplifies hardware design and extends the bandwidth ceiling beyond their existing nRF9151 LTE-M / NB-IoT / NB-NTN offering. <img src="https://s3-us-west-1.amazonaws.com/wevolver-project-images/froala%2F1784310287216-lgNordic+nRF93M1.png" width="287" class="fr-fic fr-dii" style="width:515px;height:505.721px" />Product: nRF93M1. Source: NordicIn an effort to simplify Cat 1 bis adoption, Nordic built the nRF93M1 around a single-antenna architecture, where the modem, RF front-end, and power management are all integrated into a single module with a feature set enabling optimized and robust designs. Nordic also built the nRF93M1 to support flexible SIM options, letting teams quickly choose and swap the best connectivity model for their specific deployment. Thanks to this flexible and highly integrated architecture, the nRF93M1 offers low cost of ownership and a simplified solution for Cat 1 bis deployments with pin-compatible multi-regional and global SKU options.Beyond connectivity, Nordic integrates nRF Cloud location services into the nRF93M1 to support asset tracking, covering low-power Wi-Fi positioning and cellular-based location. Fleet management, remote monitoring, and security teams can use these services to deliver location context and theft alerts alongside the connectivity payload. The nRF93M1 also features integrated observability features that let teams remotely monitor device and network parameters to identify performance issues without requiring a site visit. Long-term support is available through a CRA-certified firmware update solution, providing the compliance audit trail required to maintain IoT devices in the field.And, to support development, Nordic offers the nRF93M1 Development Kit with pre-provisioned connectivity from <a href="https://onomondo.com/?utm_campaign=campaign_%7C_nrf93_release_0826&amp;utm_medium=media&amp;utm_source=Media_Supplyframe&amp;utm_content=nordic">Onomondo</a>. The kit features Nordic’s BLE nRF54L device as a host platform. Onomondo's non-steered SIM technology pairs with the nRF93M1 to ensure devices connect to the strongest available 4G network at each location, rather than being locked to a predetermined operator by roaming agreements, maximizing the power efficiency gains Cat 1 bis is designed for. This pre-provisioned connectivity approach is a true enabler for single-SKU global deployment: one hardware design, one SIM, and consistent coverage wherever LTE exists. Backed with the open-source nRF Connect SDK, including reference designs, host application examples and pre-built support for standard IoT security protocols, Nordic’s AI-assisted development flow significantly reduces deployment risk and speeds up time to market. Teams get ongoing lifecycle support through maintained firmware, updated certifications, and security patches, so products shipped today can stay compliant without needing updated  hardware.<h1>A Practical Path for Long-Term Global Connectivity</h1>As 2G networks sunset throughout Europe and other regions, IoT product teams should consider Cat 1 bis as the connectivity solution for their next generation of hardware. With <a href="https://www.nordicsemi.com/Products/nRF93M1">Nordic’s nRF93M1</a>, designers can easily integrate Cat 1 bis into their next generation IoT deployments to keep them running today and be supported for decades to come.

A Cat 1 bis platform that provides engineers with a practical path for long-term Global connectivity.

Nordic Semiconductor Makes the Case for Cat 1 bis in IoT

Engineering reference for high voltage, high-current power conversion.

IGBT: Insulated Gate Bipolar Transistor Guide

RECOM scales power architectures without sacrificing performance or reliability

Simplifying Power Architectures with Integrated Modules and Validated Discrete Components

Understanding gate-driver fundamentals, architectures, drive techniques for SiC MOSFETs and GaN HEMTs, protection features,  key specifications, and selection guidance for modern power electronics.

Gate Driver Design for Modern Power Electronics

<h2 id="isPasted">Reliability is a Design Discipline</h2>Much of semiconductor innovation is measured by what a device can do at its limits. SimpleChips measures innovation by what a system can be trusted to do over time.With high-voltage, electronics problems surface slowly through drift, nonlinearity, thermal behavior, or edge conditions that only appear after years in the field. In critical systems, from electrified powertrains to medical devices, these effects often outweigh peak performance. They determine whether a system remains predictable, serviceable, and safe long after it has been deployed.SimpleChips was built around this reality. One of the company’s focuses is on high-voltage mixed-signal ICs for environments where tolerance stackups, component aging, and system-level interactions define success or failure. Its work is shaped by applications where reliability is not a specification but a requirement, and where simplifying a system adds value by making it more reliable.That perspective is grounded in experience. It reflects decades of experience designing and manufacturing silicon for demanding environments, and a deliberate choice to work on problems few others are willing or able to address.<h2>Reliability Understanding Starts Where Things Broke</h2>This systems-oriented mindset is closely tied to the background of SimpleChips’ founder, CEO, and CTO, Alain R. Comeau (M. Sc.). Trained as a physicist at the University of Sherbrooke, Mr. Comeau began his career inside semiconductor fabrication facilities, working in yield engineering and process integration. Those early years left a lasting impression.Working in fabs meant tracing problems from observed symptoms back to their root causes. It meant seeing how small variations in process or design assumptions could propagate into field failures. Mr. Comeau often describes this as “detective work,” an exercise which forces engineers to look beyond nominal operation and focus on where systems break down. Over time, this experience built a global view of semiconductor behavior across design, manufacturing, and long-term reliability.That perspective, and the related successes attached to it, later carried into senior technical roles across multiple organizations (Mitel, EG&amp;G, Zarlink, Microsemi), where Mr. Comeau was responsible for resolving process and yield issues from design to production. The cumulative effect of that work was a clear understanding of how tightly yield and reliability are linked, especially at the moment a product enters service.<img src="https://s3-us-west-1.amazonaws.com/wevolver-project-images/froala%2F1768403654641-1768403654641.jpeg" width="604" height="404" class="fr-fic fr-dii" alt="Alain R. Comeau (M. Sc.), Founder, CEO, and CTO at SimpleChips (Credit: SimpleChips)" />Alain R. Comeau (M. Sc.), Founder, CEO, and CTO at SimpleChips (Credit: SimpleChips)<h2>Beyond the Design Kit: When Physics Defines the Real Limit</h2>SimpleChips operates on the premise that design and manufacturing decisions must be evaluated together. Technology selection is guided by a disciplined assessment of risk, performance, and cost across the full lifecycle of a device. Improving yield is viewed as a direct path to improving reliability, particularly at time zero.This way of thinking also directly impacts how SimpleChips approaches analog and mixed-signal designs. Many engineers work within the boundaries defined by standard process design kits. These kits provide structure and consistency while also defining what is considered feasible. SimpleChips routinely questions those boundaries when application requirements demand it.According to Mr. Comeau, the limitations are not always a limitation of physics. It is more sometimes the result of constraints imposed by tooling and preexisting established libraries. When required, the team extends the process’ components’ libraries by developing new resistive, capacitive, or transistor structures, guided by a clear understanding of the risks involved and supported by extensive internal libraries built over time.<h2>Simpler Architectures for Reliability</h2>SimpleChips’ devices are designed for use in EV powertrains, industrial systems, medical equipment, and aerospace applications. These systems operate across wide voltage and temperature ranges. They are also expected to perform consistently over decades.One example illustrates how this thinking translates into silicon. In developing a high-voltage monitor, SimpleChips needed a monolithic resistor network capable of maintaining an extremely good linearity of +/-0.1% from 0 to 1200 volt (or less than +/-0.60ppm/V). Mr. Comeau stated that such a unique component (p/n 18SCT005) allows designers to build accurate and compact high-voltage sensing networks without the use of bulky external components such as high-voltage resistors or strings of low-voltage resistors. He also acknowledged that while this innovation “would not win a Nobel Prize,” its value lies in its practicality.The 18SCT005 enables simpler system architectures that would otherwise require large networks of discrete components, each introducing additional tolerances and potential failure points. By integrating this behavior into silicon, SimpleChips simplifies high-voltage sensing and improves system predictability and compactness. Engineers evaluating these devices can reference detailed performance data published on the company’s website to assess suitability for their applications.<img src="https://s3-us-west-1.amazonaws.com/wevolver-project-images/froala%2F1768403872647-Screenshot+2026-01-14+151635.png" width="299" height="398" class="fr-fic fr-dii" alt="The 18SCT005 high-voltage precision monitor IC (Credit: SimpleChips)" />The 18SCT005 high-voltage precision monitor IC (Credit: SimpleChips)<h2>Solving the Near-Impossible and Delivering the Essential</h2>SimpleChips’ current product direction is rooted in a long history of custom ASIC development. Founded in 2002, the company initially focused on IP development and licensing before transitioning in 2015 to IC manufacturing and expanding operations from Canada to the United States. Over the years, SimpleChips has built a strong reputation in enabling custom solutions for end-of-life products and legacy systems. Several of these solutions (40+) were innovative enough to warrant successful patent applications. As a result of these strong credentials and reputation, SimpleChips can now count on some of the largest U.S. system manufacturers as returning Customers.These returning Customers demanded more than component-level expertise. They demanded system-level understanding. These “resurrected chips” simply have to be dropped into existing unchanged systems and work the very first time. Inputs, outputs, timing relationships, and environmental constraints all have to be considered. This work shaped the company’s ability to deliver digital, analog, and mixed-signal functionality within tightly constrained systems on-time.<h2>Good Information Leads to Good Decisions</h2>Certain patterns of information have emerged across products, and clear challenges have appeared repeatedly. As Mr. Comeau puts it, “good information leads to good decisions”. As a result of good information, better solutions have been created. Problems exist as a result of a chain of events such as “problemA = eventB and eventC.” If eventB is eliminated, then problemA can never happen. This rationale was fundamental in understanding root-causes behind some of the most complex problems SimpleChips has resolved.SimpleChips began to formalize these recurring solutions into standard products, building a product and technology portfolio grounded in real applications. The 18SCT005 reflects this evolution. It replaces tens or hundreds of discrete resistors with a single drop-in IC, reducing assembly complexity and minimizing potential failure points. These positive impacts are equally felt at the system level. Designs become easier to validate and maintain. This improves system reliability. The value becomes what is removed from the system rather than what is added.<h2>Engineering with Consequences</h2>The environments where SimpleChips’ devices operate leave little room for error. Some of these devices are used in medical systems implanted in the human body. One chip has been deployed in defibrillators for a decade, where its purpose is to restart the heart, without a single failure.Mr. Comeau has spoken candidly about the responsibility that comes with such applications. Failure in this context carries direct human consequences. This reality reinforces the company’s emphasis on rigor, accountability, and careful decision-making. Engineering choices are made with a clear understanding of where devices will be used and what is at stake.<img src="https://s3-us-west-1.amazonaws.com/wevolver-project-images/froala%2F1768403654763-1768403654763.jpeg" width="528" height="298" class="fr-fic fr-dii" alt="High-voltage monitoring in implantable cardiac devices like pacemakers (Credit: SimpleChips)" />High-voltage monitoring in implantable cardiac devices like pacemakers (Credit: SimpleChips)<h2>Redefining the “Company”</h2>SimpleChips operates a small international team of professionals. The cultural perspective, brought in by professionals coming from 8 different countries, is viewed as sources of technical breadth and innovation. Mr. Comeau often reflects on the meaning of the word “company” as meaning to “work in the company of others”. This definition considers Customers as colleagues for the purpose of a project. Customer interaction plays a defining role in how SimpleChips operates. The company prioritizes rapid response and treats communication as an engineering input. Customers are included in feedback loops, and their insights shape both architecture and product direction. Although syntactically incorrect, SimpleChips always capitalizes the “C” in “Customers” because Customers are the most important “working-in-company-of” team member and always drive business forward.<h2>Long-Term Engineering and Reliable Electrification</h2>From a business standpoint, SimpleChips maintains both custom and standard product lines. This dual structure provides financial stability and reduces sensitivity to market fluctuations. Custom projects continue to shape product development, while standard products expand the company’s reach. This balance enables long-term engineering investment. It allows the company to focus on solving difficult problems without being driven by short-term cycles.Against this backdrop of continuous investment, power management continues to drive the electronics landscape. Electrification across transportation, industries, and infrastructures (AI) are accelerating. SimpleChips operates as an enabler within this evolution, with precision, stability, and reliability as core priorities.Mr. Comeau often speaks about positive creativity, teamwork and the responsibility that comes with building technologies for critical systems. SimpleChips’ work reflects that outlook. It is shaped by experience, informed by real applications, and guided by a clear understanding of what is at stake and what is important (root-causes) when failure is not an option.To see detailed performance data and explore the SimpleChips product portfolio, visit <a href="https://www.simplechips.com/" target="_blank">simplechips.com</a>

How SimpleChips designs high-voltage silicon for systems that must perform reliably over decades?

SimpleChips: A Systems-First Approach to High-Voltage IC Design

In the world of electronics, different industries operate on different timelines and iteration cycles. In the industrial sector, equipment is designed to operate reliably for 30 or 40 years. But in the semiconductor industry, driven by consumer demand, a "long lifecycle" is measured in single digits.When these two timelines collide, the result is component obsolescence. For an industrial engineer, a discontinued part is a crisis. For the semiconductor manufacturer, it is often just a necessary evolution of their business model. Reconciling these differences requires understanding the hidden mechanics of the semiconductor supply chain.<h2>The Black Box of Discontinuation</h2>To the outside world, a Last Time Buy (LTB) notice feels sudden. However, inside an original component manufacturer (OCM), the road to obsolescence is a long, calculated process (2). By the time a customer receives a discontinuation notice, the decision was likely made six to nine months prior.This silent phase creates a dangerous blind spot. While industrial OEMs are planning decades of maintenance, OCMs are making irreversible decisions based on quarterly efficiency and fabrication capacity. These variables rarely operate in isolation. One can usually trace every discontinued component back to one or more of four major causes: the silicon process, the package, the tester platform, or insufficient revenue (1).<h2>The Four Causes of Obsolescence</h2>While every End-of-Life (EOL) announcement seems unique, they all come from a combination of the following pressures:<h3>The Silicon Process (Wafer Technology)</h3>This is the most terminal form of obsolescence. When a foundry or Integrated Device Manufacturer (IDM) decides to shut down a specific wafer line (e.g., moving from 8-inch to 12-inch wafers or retiring a specific lithography node), the entire portfolio built on that process dies with it. There is no easy fix. Once the tooling is decommissioned, requalifying the product on a new line is often cost-prohibitive.<h3>Package Evolution</h3>The physical housing of the chip is as volatile as the silicon inside. The industry has aggressively moved away from leaded, easy-to-solder packages toward high-density BGA and QFN assemblies. Even if the silicon die is still available, the discontinuation of a specific PLCC or DIP package forces a complete board redesign and a cascade of signal-integrity testing.<h3>The Tester Bottleneck</h3>Often overlooked, the test platform is a major point of failure. Testers are expensive assets. When an OCM or assembly house migrates to a new generation of test equipment, porting legacy test programs to the new platform takes significant engineering hours. If a low-volume industrial part cannot justify the cost of that migration, it gets left behind.<h3>Economic Viability</h3>Ultimately, fab space is finite. A legacy product line must compete for clean-room real estate against newer, higher-margin components. If a device fails to meet internal revenue thresholds or profitability targets, it creates an "opportunity cost" for the OCM. Discontinuing the part clears the way for more profitable volume.All things considered, obsolescence is rarely about the part "failing." It is about the ecosystem around the part, moving on without it.<h2>Rochester’s Proactive Strategy</h2>The traditional response to obsolescence is reactive; scramble to buy stock once the LTB notice arrives. However, because the OCM’s decision process starts months earlier, the most effective strategy is actually proactive engagement.<h3>Proactive Inventory Preservation</h3>Even before full replication becomes necessary, inventory preservation can mitigate risk. During the discontinuation cycle, Rochester purchases authorized stock directly from the OCM to extend availability beyond the last-time ship date. This approach maintains traceability, offers environmental integrity, and provides a buffer for customers while they develop longer-term strategies.Inventory preservation also supports smaller OEMs that lack the purchasing power to secure extended allocations directly from the OCM. By aggregating demand across markets, Rochester can justify larger buys and maintain inventory that serves multiple end users facing the same EOL component.<h3>Licensed Manufacturing as a Long-Term Safeguard</h3>When supply from the OCM has ended, licensed manufacturing continues to support ongoing demand. Rochester’s manufacturing operation encompasses design transfer, wafer processing, assembly, and final test, all of which are performed within an authorized framework that maintains original part numbers and electrical equivalence.This capability allows customers to continue sourcing devices that are electrically and mechanically identical to the originals, supported by the same test data and specifications. For industries constrained by certification requirements, that distinction is huge. A replicated or remanufactured part that is functionally identical ensures compliance without triggering the regulatory or software cascade of a redesign.<h2>Case Study: The Intel 82527 Transition</h2>A prime example is when Rochester partnered with Intel on their discontinued 82527 CAN controller (3). This component was a staple in automotive and industrial communication systems for over a decade.When Intel decided to exit the market for this specific controller, the demand from industrial customers did not vanish. In 2005, rather than leaving customers to redesign their systems, Intel transferred the product line to Rochester Electronics.By assuming the authorized manufacturing role, Rochester preserved the controller’s availability long after Intel exited the market. By maintaining continuity, Rochester allowed system manufacturers to avoid expensive redesigns and to maintain support for equipment that relied on a well-validated communication standard.Rochester applies the same model across a wide portfolio of devices where demand persists beyond an OCM’s commercial horizon. Licensed manufacturing, when coupled with preserved die stock and archival test data, lets industrial customers sustain production without deviation from original specifications.<h2>The Takeaway</h2>Industrial engineers cannot stop the clock of semiconductor innovation, but they can decouple their equipment from it. By understanding the root causes of discontinuation and partnering with authorized sources for licensed manufacturing, organizations can prevent obsolescence from becoming an existential threat.<iframe width="540" height="450" src="https://c8056756.sibforms.com/serve/MUIFAFt1_uNZMl0gRdqIpx2bkxdyopcpqLsCtYcPhp2zo0lodsS0XFN1pA4wkISL9Pp7bXqab9UifXxpwu0HD7C4Tk1M0xW6IVGDpEiruQB8ArvAR6LYsO3o_M1x1xmjlpjU3cRBrWR3Zr4Ufcb95Mz5JYK4hbCUcQFTj9urfN5lXD6Bb52-mLUeCxft7hVXmD07kwWTRw7oEijI" frameborder="0" scrolling="auto" style="display:block;margin-left:auto;margin-right:auto;max-width:100%"></iframe> <h2>References</h2>1. <a href="https://www.wevolver.com/article/the-causes-of-component-obsolescence" target="_blank">https://www.wevolver.com/article/the-causes-of-component-obsolescence</a>2. <a href="https://rocelec.widen.net/s/nlqh7jxbks/esna-feb24-p14-rochester17" target="_blank" rel="noopener noreferrer">https://rocelec.widen.net/s/nlqh7jxbks/esna-feb24-p14-rochester17</a>3. <a href="https://www.rocelec.com/news/can-bus-support?utm_campaign=11081481-Jun25-English-Legacy" target="_blank" rel="noopener noreferrer">https://www.rocelec.com/news/can-bus-support</a>

When Industrial Longevity Meets Semiconductor Speed: The Root of Component Obsolescence

Why Semiconductor Components Exit the Market?

A comprehensive overview of fully depleted silicon on insulator technology, covering device physics, process nodes and practical design approaches to help digital and hardware engineers leverage FDSOI for low power, high performance, and RF/mm wave applications.

Fully Depleted Silicon on Insulator (FDSOI) Theory, Design and Applications for Modern Engineers

Modern compute systems are constrained less by what they can do and more by what they can sustain. From edge sensing devices and industrial wearables to data centers and space systems, the boundaries of what engineers can build are defined by power, thermal limits, and system longevity. In other words, energy is the fundamental constraint.As demand grows for AI-driven functionality in embedded and remote systems, engineers must deliver more capability within shrinking power and thermal budgets. At the edge, devices must operate for months or years without maintenance. In space, energy is limited, heat dissipation is difficult, and reliability must be engineered into every component.Traditional processors are not built for this context. They are designed to run general-purpose workloads across a wide range of applications, often to remain compatible with software written decades ago. As Efficient Computer describes it, conventional CPUs “are overdesigned for generality”.This approach has led to architectures that are large, complex, and power hungry. Much of the energy consumed goes not into useful computation but into internal data movement and instruction control.The result is a growing mismatch between the capabilities of modern compute systems and the physical limitations of their deployment environments. The industry is now reaching the point where performance per watt has become the defining metric. The question is no longer how much raw power a processor can deliver, but how efficiently it can do the work that matters within the limits of real-world systems. This shift demands a rethinking of compute architecture.<h2>Compute Design Reconsidered</h2>If energy defines the limits of modern compute systems, then architectural design must treat efficiency as a first principle. With the rise of embedded and remote applications, the goal has become sustained performance in environments where power is scarce, heat must be avoided, and resilience matters as much as speed.This reframing exposes the limits of current strategies. Many modern SoCs try to save power with fixed-purpose accelerators, but workloads change faster than hardware can. When an accelerator does not match the task, execution falls back to a power‑hungry CPU core, leading to dormant hardware and unrealised energy efficiency.<a href="https://www.efficient.computer/announcing-electron-e1-processor">Efficient Computer</a> approaches this problem from first principles. This US‑based chip startup is building a new class of processors for systems that must deliver high‑value compute within strict energy, thermal, and reliability constraints. Its first product, the Electron E1 processor, is the world’s most energy-efficient, general-purpose system-on-chip. Designed for battery‑powered, embedded, and remote deployments, the E1 processor pairs ASIC‑class efficiency with general-purpose programmability.<a href="https://www.efficient.computer/announcing-electron-e1-processor">The Electron E1 processor</a> runs complete applications with exceptional energy performance. Neural networks, digital signal processing, graph analytics, compression, and cryptography all execute locally without reliance on narrow accelerators or cloud offload. The result is responsive, private, and reliable compute where power is limited, and connectivity is unreliable or unavailable.These capabilities rest on Efficient’s proprietary Fabric architecture. Programs execute as dataflow graphs across a spatial compute array, eliminating much of the control and hierarchy overhead found in conventional processors. The Electron E1 processor moves the compute closer to the data. Products can process information locally, efficiently, and intelligently. For designers facing hard limits on space, heat, and power, it opens a path to embedded intelligence that was previously out of reach.<img src="https://s3-us-west-1.amazonaws.com/wevolver-project-images/froala%2F1753290091800-E1_Data+graph-02+%281%29.png" style="width:100%px" class="fr-fic fr-dib" /><h3 id="isPasted">The Architecture That Makes It Possible</h3>The Fabric architecture behind the Electron E1 processor is an energy-minimal dataflow architecture. It implements spatial parallelism and a distributed structure of Processing Elements (PEs) that eliminates much of the overhead found in traditional CPU designs. Each PE executes operations as soon as data is available, following a data-driven execution model. Instruction memory is distributed throughout the Fabric network in the form of bitstream caches.The design avoids speculative execution, global clock distribution, and deep cache hierarchies. Simplicity lowers leakage current and switching activity, two primary sources of wasted power. Direct tile‑to‑tile links keep communication short and predictable, which tightens performance control and eases timing closure.To support complete applications on‑device, the Electron E1 processor integrates fast local memory and rich peripherals within the same low‑power envelope, as shown in the table below.<div><table><tbody><tr><td>Feature</td><td>Purpose</td></tr><tr><td>4 MB MRAM</td><td>Holds firmware and large data sets on‑chip, eliminating high‑energy off‑chip storage accesses</td></tr><tr><td>3 MB SRAM</td><td>Provides fast working memory for Fabric tiles without the power cost of external DRAM</td></tr><tr><td>128 KB cache</td><td>Captures temporal data reuse, reducing tile‑to‑tile traffic and further cutting energy per operation</td></tr><tr><td>Six UART ports</td><td>Connects to sensors or radios with minimal protocol overhead and predictable timing</td></tr><tr><td>Six QSPI masters</td><td>Streams high‑bandwidth data, such as camera frames, into Fabric without external DMA logic</td></tr><tr><td>Six SPI‑slave interfaces</td><td>Provides high‑speed host communication without extra bridge logic or power overhead</td></tr><tr><td>Six I²C masters</td><td>Manages low‑speed peripherals and configuration buses while keeping wiring simple</td></tr><tr><td>Seventy‑two GPIOs</td><td>Offers broad digital I/O without extra expanders, saving board area and leakage current</td></tr><tr><td>On‑chip RTC</td><td>Enables precise wake‑sleep scheduling for long duty cycles without an external timer</td></tr><tr><td>Programmable power‑management unit</td><td>Dynamically scales voltage and frequency, matching energy use to workload demand</td></tr><tr><td>Integrated regulators and clock generation</td><td>Removes external PMIC and oscillator components, shrinking PCB footprint, and lowering total system power</td></tr></tbody></table></div>The Electron E1 processor delivers up to 100x the energy efficiency of conventional low-power CPUs and can operate for years on small batteries or harvested power. This is the foundation that allows engineers to deploy local intelligence where it was previously not feasible.<blockquote>The Electron E1 processor and effcc Compiler are built from the ground up to deliver radically better energy efficiency for general-purpose computing applications. Our spatial dataflow design means that developers no longer have to choose between efficiency and generality. With this release, we’re enabling the next generation of energy-constrained computing applications and devices.”—Brandon Lucia, Efficient Computer, CEO.</blockquote>Architecture and application are inseparable. In sealed industrial enclosures, reduced data movement limits heat rise and allows fanless designs. In orbit, deterministic operation and low leakage support reliable missions under tight power budgets. The Electron E1 processor shows that when efficiency becomes the design foundation, intelligent systems can live where power, heat, and maintenance once stood in the way.<img src="https://s3-us-west-1.amazonaws.com/wevolver-project-images/froala%2F1753290159668-EFFCC+Compiler+-comuter+graphic.png" style="width:100%px" class="fr-fic fr-dib" /><h2 id="isPasted">Software That Meets Developers Where They Are</h2>Energy‑first hardware delivers value only if the software path is clear. Efficient Computer built that path in parallel with the silicon through the effcc® Compiler, a dataflow compiler that maps conventional code onto the Fabric processor with speed and precision.<a href="https://www.efficient.computer/announcing-electron-e1-processor">The effcc Compiler</a> is fully compatible with standard C, allowing developers to work within familiar toolchains; upcoming releases add ONNX, C++, Python, and Rust. Developers stay inside existing toolchains while effcc replaces GCC or Clang in the build flow. Compilation completes in seconds, giving teams rapid feedback without FPGA‑style synthesis delays.The effcc Compiler automatically transforms high-level code into a dataflow graph, mapping it onto the Fabric architecture with optimizations for locality and parallelism. There is no need to learn a new programming language. As one of Efficient’s engineers put it, “The effcc Compiler takes your code, converts it into a dataflow graph, and optimizes it for maximum efficiency on the Fabric processor.”Among the core technologies powering the effcc Compiler is MOF®, an optimizer that analyses where a program spends energy and restructures it as a dataflow graph tuned for Fabric. It exposes parallelism, places data close to compute, and selects the lowest‑energy execution pattern without requiring manual refactoring.The surrounding toolset includes a drop‑in debugger, a functional simulator, and power‑estimation utilities. Together, they let developers move from initial compile to energy profiling in a single workflow.This has practical implications for teams working in embedded applications:●   An industrial wearable running multiple AI models keeps its full feature set because each inference passes through Fabric with minimal overhead.●   A field robot executes local decision logic all day on a modest battery and stays cool enough for sealed housing.●   A remote sensor stack blends signal processing and compression on‑device, trimming wireless data volume and extending battery life.The effect turns the Fabric into a ready target for production software, rather than a research platform. Teams can bring existing code, iterate fast, and deploy systems that meet strict power and thermal budgets without trading away capability.<h2>Design Stories in the Field</h2>Architecture earns its value when it expands what engineers can build. The three examples below show where the Electron E1 processor delivers capabilities that were previously out of reach.<h3>Industrial Automation</h3>Industrial sensors and embedded controllers often sit inside sealed housings where batteries must last for years, and heat has nowhere to escape. The Electron E1 processor lets these nodes perform vibration analysis, sensor fusion, and anomaly detection locally, sampling at high rates without overrunning the energy budget.A single battery or an energy harvesting module is enough to power continuous inference, while the chip’s deterministic timing keeps results predictable for maintenance planners. Real computation now lives inside spaces once limited to simple threshold triggers.<h3>Space Systems</h3>Space-grade computers must be radiation-tolerant, power-efficient, and highly reliable. The deterministic, low-leakage nature of the Fabric architecture reduces complexity and failure points.Whether embedded in a CubeSat, a planetary lander, or a high-orbit surveillance platform, the Electron E1 processor reliably provides attitude determination, image compression, and autonomy functions in milliwatts, easing thermal design and extending mission life when solar input is low. Engineers gain general‑purpose processing without the mass and power penalties that usually accompany reliability in space.<h3>Industrial Wearables</h3>Computer vision, environmental sensing, and AI-assisted feedback are becoming standard in industrial safety and productivity gear. The challenge is to fit these capabilities into wearable devices that must be lightweight, safe, and battery-efficient.The Electron E1 processor runs multi-modal AI models at the edge of the network, tracking hazards or worker fatigue in real time while remaining under human-safe surface temperatures. A full work shift on a small lithium‑ion battery is realistic, and the absence of bulky heat sinks keeps devices comfortable and unobtrusive. Concepts move from lab demo to field deployment without a trade‑off between intelligence and ergonomics.<h2>Deployment, Design Guidance, and What Comes Next</h2>The Electron E1 processor has been engineered for integration into embedded and robotics systems with minimal friction. In typical operation, the chip operates in milliwatts, and its thermal profile stays within the limits of sealed enclosures and body‑mounted wearables. The on-chip power-management unit, integrated regulators, and local clock generation reduce board complexity.The roadmap builds on the same principle that shaped the first device: energy is the anchor, not an optimization pass. The Fabric architecture scales horizontally across multiple chips for higher throughput. Future releases will retain programmability, efficiency, and simplicity as first-order principles.For engineers who live with tight limits on power, space, and maintenance, the choice of architecture defines what’s possible. By cutting wasted data movement and aligning compute with the available energy, the Electron E1 processor turns constraints into design headroom. Systems that once relied on cloud resources or custom ASICs can now run locally, efficiently, and with room to evolve.To learn more about the Electron E1 processor, the Fabric architecture, or the effcc Compiler, visit <a href="https://www.efficient.computer/announcing-electron-e1-processor">Efficient Computer</a> and join the product launch program.<h1>References</h1>1. A. Shilov, “Startup aims to make CPUs 100x more energy efficient with ‘reconfigurable’ chips - Efficient Computer reveals…,” Tom’s Hardware, Mar. 08, 2024. [Online]. Available:<a href="https://www.tomshardware.com/pc-components/cpus/startup-aims-to-make-cpus-100x-more-energy-efficient-with-reconfigurable-chips"> https://www.tomshardware.com/pc-components/cpus/startup-aims-to-make-cpus-100x-more-energy-efficient-with-reconfigurable-chips</a>

Traditional processors are inefficient in certain contexts, wasting energy on data movement rather than computation. As a result, the industry is shifting focus to maximizing performance per watt, highlighting the need to rethink compute architecture to meet real-world constraints.

Designing in Milliwatts: Rethinking Compute Architecture with the Electron E1 Processor

Artificial intelligence is advancing at a faster rate than the hardware designed to support it. Every leap in model complexity and training scale pushes GPUs and TPUs closer to their physical and thermal limits.&nbsp;As data centres expand and edge devices become more powerful, the question is no longer how to build bigger AI systems; it’s how to run them efficiently. The current bottleneck? Power consumption, latency, and heat. But what if electrons aren’t the future of AI computation? What if photons could shoulder the load?That’s the provocative challenge being answered by NeuroCore, one of the standout entrants in the recently completed PhotonDelta Global Photonics Engineering Contest. Their concept: a photonic neural network accelerator built on a hybrid photonic integrated circuit. By performing matrix operations using light, not charge, the design aims to deliver high-speed, low-power computation for AI workloads that are outpacing traditional silicon. It doesn’t enter as a direct GPU replacement. It’s a rethink of what AI acceleration should be.<h2>The Growing Bottleneck in AI Hardware</h2>As AI models continue to scale, from GPT-class language models to real-time vision systems in autonomous vehicles, the hardware load grows exponentially. The root cause is a single operation repeated billions of times per second: the multiply-accumulate (MAC). These operations form the core of matrix multiplication, the heart of neural network inference and training.GPUs and TPUs are designed to execute these operations in parallel. However, parallelism in the electrical domain comes at a cost: high clock rates, resistive heating, and substantial energy consumption. In large-scale data centres, this results in mounting electricity bills and substantial cooling demands. For edge devices, thermal ceilings and battery constraints limit performance.Even with advanced lithography and architectural enhancements, conventional chips are reaching a limit. More transistors mean more heat. Higher clock speed means higher power consumption. AI's needs are rising faster than Moore's Law can keep pace with.This growing mismatch between computational demand and electronic capability is fuelling interest in a different class of hardware: photonic accelerators.<h2>Spotlighting the NeuroCore Concept: Photonic Neural Network Acceleration</h2>NeuroCore's approach begins by abandoning charge carriers in favour of photons. Their proposed accelerator utilizes light to perform core neural network operations, specifically matrix multiplication, through optical interference.At the centre of this design are Mach-Zehnder interferometers (MZIs), which control the phase and amplitude of light traveling through waveguides. When configured in a mesh, these MZIs can encode weights and simulate the behaviour of a neural network layer. Instead of moving electrons, the system splits and combines coherent light beams, with interference patterns effectively performing the mathematical operations.This technique, known as interference-based computing, offers two critical advantages: parallelism and speed. Light can travel along multiple paths simultaneously without interference (in the disruptive sense), and does so at, well, the speed of light. As a result, the NeuroCore mesh can handle multiple MAC operations simultaneously, with no clock overhead.The system doesn’t go fully optical—electronics still play a crucial supporting role. Hybrid control circuits manage calibration, feedback, and the non-linear activation functions that follow optical matrix operations. Moreover, because most downstream systems and interfaces remain electronic, the processed optical signals must eventually be converted back into the electrical domain. This hybrid architecture—optical compute with electronic oversight—blends the speed and parallelism of light with the precision, tunability, and interoperability of electronics.<h2>System Architecture and Technical Design</h2>The NeuroCore system is built on a tri-material stack consisting of silicon photonics (SiPh), silicon nitride (SiN), and indium phosphide (InP). Each material serves a specific role, chosen for performance and manufacturability.The light source originates from an InP laser diode. InP is the only one of the three with a direct bandgap, making it ideal for efficient light generation. The laser couples into the waveguide mesh through an optimized interface designed to minimize insertion loss.From there, the light enters the heart of the system: a configurable mesh built from SiN and SiPh waveguides and couplers. The SiN component is critical for maintaining signal strength. Its ultra-low propagation loss enables long path lengths without degrading optical power, essential when light must pass through dozens or hundreds of interferometers.The SiPh layer brings dynamic functionality. Silicon’s electro-optic properties enable phase shifting via electrical signals, allowing network weights to be programmed and updated in real-time. Phase shifters on each MZI arm allow real-time reconfiguration of the optical matrix.At the output, integrated photodiodes convert the optical signals back into electrical form. This stage closes the loop, feeding processed data into external systems or storage. Alongside the mesh are control electronics, including drivers, calibration feedback systems, thermal stabilizers, and readout modules, that ensure consistent and accurate behavior under real-world conditions.<img src="https://s3-us-west-1.amazonaws.com/wevolver-project-images/froala%2F1753121809135-flow+chart.jpg" style="width: 100%px;" class="fr-fic fr-dib">System Design - Flowchart and/or Block Diagram | Source: NeuroCore Photonic Integrated Neuron Chip Submission&nbsp;In short, it’s a complete optical MAC engine, backed by precision electrical tuning, modular, programmable, and ready to scale.<h2>Applications in AI, ML, and High-Performance Systems</h2>The immediate applications for this technology are in environments where AI inference needs to be fast, power-efficient, and scalable. Data centres are the obvious starting point. By offloading key layers of a deep neural network to photonic meshes, server clusters can reduce heat output and energy draw without compromising throughput.Edge AI is another compelling use case. In self-driving cars, for example, photonic inference engines can process lidar or camera data in real-time without overheating the system or draining the battery. Similarly, in medical diagnostics, where speed and accuracy are crucial, optical neural networks could enable faster and more responsive cancer detection tools.Photonic acceleration also aligns with broader sustainability goals. As AI becomes a baseline utility, the energy costs of computation matter more than ever. Reducing per-inference energy use at scale could significantly decrease the carbon footprint of machine learning.And because the design is modular, the system can scale with model size. Larger networks can be mapped to larger meshes. Photonic layers can be stacked or tiled. Unlike traditional chip designs, this mesh doesn’t require rethinking the architecture with every increase in model parameter count.<h2>Feasibility and Roadmap Ahead</h2>NeuroCore’s project is currently in its research and planning phase. The team has completed a rigorous evaluation of photonic neural network design principles, material compatibility, and system architecture. The focus is now on simulation: modelling mesh behaviour, optimizing phase control circuits, and evaluating insertion losses across key paths.One of the early challenges is the fabrication process. Integrating SiN, SiPh, and InP on a single chip requires precise alignment and bonding techniques to ensure optimal performance. This hybrid integration is achievable but demands advanced packaging workflows. Another challenge is stability. Optical systems are sensitive to temperature variations, so maintaining phase coherence requires real-time feedback and thermal compensation.Fortunately, ecosystems like PhotonDelta are built to accelerate this kind of development. Access to fabrication pipelines, design support, and industry mentoring will be crucial in transforming NeuroCore’s early-stage design into a functional prototype. With the right partnerships, the accelerator could transition from concept to chip far quicker than most standalone efforts.<h2>Conclusion: Lighting the Path to Scalable AI</h2>AI isn’t slowing down, but our current hardware might. As neural networks grow deeper and data volumes balloon, the pressure on electrical systems to keep pace is becoming unsustainable. Photonic computing is becoming a necessity, not an alternative.NeuroCore’s submission to the PhotonDelta Global Photonics Engineering Contest outlines a compelling future: scalable, energy-efficient, high-speed AI acceleration built on the principles of light physics. The designed hybrid photonic chip reimagines how and where computation happens.As AI capabilities expand, the supporting infrastructure must also evolve. Innovations like this suggest that the future of artificial intelligence may rely not only on traditional silicon, but also on the integration of photonic technologies.

What if electrons aren't the future of AI computation? What if photons could shoulder the load?

How Integrated Photonics Could Redefine Machine Learning Efficiency

This article examines microcontroller vs microprocessor architectures at the system level, explaining how their hardware resources, boot requirements, software stacks, and application demands differ.

Microcontroller vs Microprocessor: The Real Differences

Nordic Semiconductor