A comprehensive overview of fully depleted silicon on insulator technology, covering device physics, process nodes and practical design approaches to help digital and hardware engineers leverage FDSOI for low power, high performance, and RF/mm wave applications.

Fully Depleted Silicon on Insulator (FDSOI) Theory, Design and Applications for Modern Engineers

Modern compute systems are constrained less by what they can do and more by what they can sustain. From edge sensing devices and industrial wearables to data centers and space systems, the boundaries of what engineers can build are defined by power, thermal limits, and system longevity. In other words, energy is the fundamental constraint.As demand grows for AI-driven functionality in embedded and remote systems, engineers must deliver more capability within shrinking power and thermal budgets. At the edge, devices must operate for months or years without maintenance. In space, energy is limited, heat dissipation is difficult, and reliability must be engineered into every component.Traditional processors are not built for this context. They are designed to run general-purpose workloads across a wide range of applications, often to remain compatible with software written decades ago. As Efficient Computer describes it, conventional CPUs “are overdesigned for generality”.This approach has led to architectures that are large, complex, and power hungry. Much of the energy consumed goes not into useful computation but into internal data movement and instruction control.The result is a growing mismatch between the capabilities of modern compute systems and the physical limitations of their deployment environments. The industry is now reaching the point where performance per watt has become the defining metric. The question is no longer how much raw power a processor can deliver, but how efficiently it can do the work that matters within the limits of real-world systems. This shift demands a rethinking of compute architecture.<h2>Compute Design Reconsidered</h2>If energy defines the limits of modern compute systems, then architectural design must treat efficiency as a first principle. With the rise of embedded and remote applications, the goal has become sustained performance in environments where power is scarce, heat must be avoided, and resilience matters as much as speed.This reframing exposes the limits of current strategies. Many modern SoCs try to save power with fixed-purpose accelerators, but workloads change faster than hardware can. When an accelerator does not match the task, execution falls back to a power‑hungry CPU core, leading to dormant hardware and unrealised energy efficiency.<a href="https://www.efficient.computer/announcing-electron-e1-processor">Efficient Computer</a> approaches this problem from first principles. This US‑based chip startup is building a new class of processors for systems that must deliver high‑value compute within strict energy, thermal, and reliability constraints. Its first product, the Electron E1 processor, is the world’s most energy-efficient, general-purpose system-on-chip. Designed for battery‑powered, embedded, and remote deployments, the E1 processor pairs ASIC‑class efficiency with general-purpose programmability.<a href="https://www.efficient.computer/announcing-electron-e1-processor">The Electron E1 processor</a> runs complete applications with exceptional energy performance. Neural networks, digital signal processing, graph analytics, compression, and cryptography all execute locally without reliance on narrow accelerators or cloud offload. The result is responsive, private, and reliable compute where power is limited, and connectivity is unreliable or unavailable.These capabilities rest on Efficient’s proprietary Fabric architecture. Programs execute as dataflow graphs across a spatial compute array, eliminating much of the control and hierarchy overhead found in conventional processors. The Electron E1 processor moves the compute closer to the data. Products can process information locally, efficiently, and intelligently. For designers facing hard limits on space, heat, and power, it opens a path to embedded intelligence that was previously out of reach.<img src="https://s3-us-west-1.amazonaws.com/wevolver-project-images/froala%2F1753290091800-E1_Data+graph-02+%281%29.png" style="width:100%px" class="fr-fic fr-dib" /><h3 id="isPasted">The Architecture That Makes It Possible</h3>The Fabric architecture behind the Electron E1 processor is an energy-minimal dataflow architecture. It implements spatial parallelism and a distributed structure of Processing Elements (PEs) that eliminates much of the overhead found in traditional CPU designs. Each PE executes operations as soon as data is available, following a data-driven execution model. Instruction memory is distributed throughout the Fabric network in the form of bitstream caches.The design avoids speculative execution, global clock distribution, and deep cache hierarchies. Simplicity lowers leakage current and switching activity, two primary sources of wasted power. Direct tile‑to‑tile links keep communication short and predictable, which tightens performance control and eases timing closure.To support complete applications on‑device, the Electron E1 processor integrates fast local memory and rich peripherals within the same low‑power envelope, as shown in the table below.<div><table><tbody><tr><td>Feature</td><td>Purpose</td></tr><tr><td>4 MB MRAM</td><td>Holds firmware and large data sets on‑chip, eliminating high‑energy off‑chip storage accesses</td></tr><tr><td>3 MB SRAM</td><td>Provides fast working memory for Fabric tiles without the power cost of external DRAM</td></tr><tr><td>128 KB cache</td><td>Captures temporal data reuse, reducing tile‑to‑tile traffic and further cutting energy per operation</td></tr><tr><td>Six UART ports</td><td>Connects to sensors or radios with minimal protocol overhead and predictable timing</td></tr><tr><td>Six QSPI masters</td><td>Streams high‑bandwidth data, such as camera frames, into Fabric without external DMA logic</td></tr><tr><td>Six SPI‑slave interfaces</td><td>Provides high‑speed host communication without extra bridge logic or power overhead</td></tr><tr><td>Six I²C masters</td><td>Manages low‑speed peripherals and configuration buses while keeping wiring simple</td></tr><tr><td>Seventy‑two GPIOs</td><td>Offers broad digital I/O without extra expanders, saving board area and leakage current</td></tr><tr><td>On‑chip RTC</td><td>Enables precise wake‑sleep scheduling for long duty cycles without an external timer</td></tr><tr><td>Programmable power‑management unit</td><td>Dynamically scales voltage and frequency, matching energy use to workload demand</td></tr><tr><td>Integrated regulators and clock generation</td><td>Removes external PMIC and oscillator components, shrinking PCB footprint, and lowering total system power</td></tr></tbody></table></div>The Electron E1 processor delivers up to 100x the energy efficiency of conventional low-power CPUs and can operate for years on small batteries or harvested power. This is the foundation that allows engineers to deploy local intelligence where it was previously not feasible.<blockquote>The Electron E1 processor and effcc Compiler are built from the ground up to deliver radically better energy efficiency for general-purpose computing applications. Our spatial dataflow design means that developers no longer have to choose between efficiency and generality. With this release, we’re enabling the next generation of energy-constrained computing applications and devices.”—Brandon Lucia, Efficient Computer, CEO.</blockquote>Architecture and application are inseparable. In sealed industrial enclosures, reduced data movement limits heat rise and allows fanless designs. In orbit, deterministic operation and low leakage support reliable missions under tight power budgets. The Electron E1 processor shows that when efficiency becomes the design foundation, intelligent systems can live where power, heat, and maintenance once stood in the way.<img src="https://s3-us-west-1.amazonaws.com/wevolver-project-images/froala%2F1753290159668-EFFCC+Compiler+-comuter+graphic.png" style="width:100%px" class="fr-fic fr-dib" /><h2 id="isPasted">Software That Meets Developers Where They Are</h2>Energy‑first hardware delivers value only if the software path is clear. Efficient Computer built that path in parallel with the silicon through the effcc® Compiler, a dataflow compiler that maps conventional code onto the Fabric processor with speed and precision.<a href="https://www.efficient.computer/announcing-electron-e1-processor">The effcc Compiler</a> is fully compatible with standard C, allowing developers to work within familiar toolchains; upcoming releases add ONNX, C++, Python, and Rust. Developers stay inside existing toolchains while effcc replaces GCC or Clang in the build flow. Compilation completes in seconds, giving teams rapid feedback without FPGA‑style synthesis delays.The effcc Compiler automatically transforms high-level code into a dataflow graph, mapping it onto the Fabric architecture with optimizations for locality and parallelism. There is no need to learn a new programming language. As one of Efficient’s engineers put it, “The effcc Compiler takes your code, converts it into a dataflow graph, and optimizes it for maximum efficiency on the Fabric processor.”Among the core technologies powering the effcc Compiler is MOF®, an optimizer that analyses where a program spends energy and restructures it as a dataflow graph tuned for Fabric. It exposes parallelism, places data close to compute, and selects the lowest‑energy execution pattern without requiring manual refactoring.The surrounding toolset includes a drop‑in debugger, a functional simulator, and power‑estimation utilities. Together, they let developers move from initial compile to energy profiling in a single workflow.This has practical implications for teams working in embedded applications:●   An industrial wearable running multiple AI models keeps its full feature set because each inference passes through Fabric with minimal overhead.●   A field robot executes local decision logic all day on a modest battery and stays cool enough for sealed housing.●   A remote sensor stack blends signal processing and compression on‑device, trimming wireless data volume and extending battery life.The effect turns the Fabric into a ready target for production software, rather than a research platform. Teams can bring existing code, iterate fast, and deploy systems that meet strict power and thermal budgets without trading away capability.<h2>Design Stories in the Field</h2>Architecture earns its value when it expands what engineers can build. The three examples below show where the Electron E1 processor delivers capabilities that were previously out of reach.<h3>Industrial Automation</h3>Industrial sensors and embedded controllers often sit inside sealed housings where batteries must last for years, and heat has nowhere to escape. The Electron E1 processor lets these nodes perform vibration analysis, sensor fusion, and anomaly detection locally, sampling at high rates without overrunning the energy budget.A single battery or an energy harvesting module is enough to power continuous inference, while the chip’s deterministic timing keeps results predictable for maintenance planners. Real computation now lives inside spaces once limited to simple threshold triggers.<h3>Space Systems</h3>Space-grade computers must be radiation-tolerant, power-efficient, and highly reliable. The deterministic, low-leakage nature of the Fabric architecture reduces complexity and failure points.Whether embedded in a CubeSat, a planetary lander, or a high-orbit surveillance platform, the Electron E1 processor reliably provides attitude determination, image compression, and autonomy functions in milliwatts, easing thermal design and extending mission life when solar input is low. Engineers gain general‑purpose processing without the mass and power penalties that usually accompany reliability in space.<h3>Industrial Wearables</h3>Computer vision, environmental sensing, and AI-assisted feedback are becoming standard in industrial safety and productivity gear. The challenge is to fit these capabilities into wearable devices that must be lightweight, safe, and battery-efficient.The Electron E1 processor runs multi-modal AI models at the edge of the network, tracking hazards or worker fatigue in real time while remaining under human-safe surface temperatures. A full work shift on a small lithium‑ion battery is realistic, and the absence of bulky heat sinks keeps devices comfortable and unobtrusive. Concepts move from lab demo to field deployment without a trade‑off between intelligence and ergonomics.<h2>Deployment, Design Guidance, and What Comes Next</h2>The Electron E1 processor has been engineered for integration into embedded and robotics systems with minimal friction. In typical operation, the chip operates in milliwatts, and its thermal profile stays within the limits of sealed enclosures and body‑mounted wearables. The on-chip power-management unit, integrated regulators, and local clock generation reduce board complexity.The roadmap builds on the same principle that shaped the first device: energy is the anchor, not an optimization pass. The Fabric architecture scales horizontally across multiple chips for higher throughput. Future releases will retain programmability, efficiency, and simplicity as first-order principles.For engineers who live with tight limits on power, space, and maintenance, the choice of architecture defines what’s possible. By cutting wasted data movement and aligning compute with the available energy, the Electron E1 processor turns constraints into design headroom. Systems that once relied on cloud resources or custom ASICs can now run locally, efficiently, and with room to evolve.To learn more about the Electron E1 processor, the Fabric architecture, or the effcc Compiler, visit <a href="https://www.efficient.computer/announcing-electron-e1-processor">Efficient Computer</a> and join the product launch program.<h1>References</h1>1. A. Shilov, “Startup aims to make CPUs 100x more energy efficient with ‘reconfigurable’ chips - Efficient Computer reveals…,” Tom’s Hardware, Mar. 08, 2024. [Online]. Available:<a href="https://www.tomshardware.com/pc-components/cpus/startup-aims-to-make-cpus-100x-more-energy-efficient-with-reconfigurable-chips"> https://www.tomshardware.com/pc-components/cpus/startup-aims-to-make-cpus-100x-more-energy-efficient-with-reconfigurable-chips</a>

Traditional processors are inefficient in certain contexts, wasting energy on data movement rather than computation. As a result, the industry is shifting focus to maximizing performance per watt, highlighting the need to rethink compute architecture to meet real-world constraints.

Designing in Milliwatts: Rethinking Compute Architecture with the Electron E1 Processor

Artificial intelligence is advancing at a faster rate than the hardware designed to support it. Every leap in model complexity and training scale pushes GPUs and TPUs closer to their physical and thermal limits.&nbsp;As data centres expand and edge devices become more powerful, the question is no longer how to build bigger AI systems; it’s how to run them efficiently. The current bottleneck? Power consumption, latency, and heat. But what if electrons aren’t the future of AI computation? What if photons could shoulder the load?That’s the provocative challenge being answered by NeuroCore, one of the standout entrants in the recently completed PhotonDelta Global Photonics Engineering Contest. Their concept: a photonic neural network accelerator built on a hybrid photonic integrated circuit. By performing matrix operations using light, not charge, the design aims to deliver high-speed, low-power computation for AI workloads that are outpacing traditional silicon. It doesn’t enter as a direct GPU replacement. It’s a rethink of what AI acceleration should be.<h2>The Growing Bottleneck in AI Hardware</h2>As AI models continue to scale, from GPT-class language models to real-time vision systems in autonomous vehicles, the hardware load grows exponentially. The root cause is a single operation repeated billions of times per second: the multiply-accumulate (MAC). These operations form the core of matrix multiplication, the heart of neural network inference and training.GPUs and TPUs are designed to execute these operations in parallel. However, parallelism in the electrical domain comes at a cost: high clock rates, resistive heating, and substantial energy consumption. In large-scale data centres, this results in mounting electricity bills and substantial cooling demands. For edge devices, thermal ceilings and battery constraints limit performance.Even with advanced lithography and architectural enhancements, conventional chips are reaching a limit. More transistors mean more heat. Higher clock speed means higher power consumption. AI's needs are rising faster than Moore's Law can keep pace with.This growing mismatch between computational demand and electronic capability is fuelling interest in a different class of hardware: photonic accelerators.<h2>Spotlighting the NeuroCore Concept: Photonic Neural Network Acceleration</h2>NeuroCore's approach begins by abandoning charge carriers in favour of photons. Their proposed accelerator utilizes light to perform core neural network operations, specifically matrix multiplication, through optical interference.At the centre of this design are Mach-Zehnder interferometers (MZIs), which control the phase and amplitude of light traveling through waveguides. When configured in a mesh, these MZIs can encode weights and simulate the behaviour of a neural network layer. Instead of moving electrons, the system splits and combines coherent light beams, with interference patterns effectively performing the mathematical operations.This technique, known as interference-based computing, offers two critical advantages: parallelism and speed. Light can travel along multiple paths simultaneously without interference (in the disruptive sense), and does so at, well, the speed of light. As a result, the NeuroCore mesh can handle multiple MAC operations simultaneously, with no clock overhead.The system doesn’t go fully optical—electronics still play a crucial supporting role. Hybrid control circuits manage calibration, feedback, and the non-linear activation functions that follow optical matrix operations. Moreover, because most downstream systems and interfaces remain electronic, the processed optical signals must eventually be converted back into the electrical domain. This hybrid architecture—optical compute with electronic oversight—blends the speed and parallelism of light with the precision, tunability, and interoperability of electronics.<h2>System Architecture and Technical Design</h2>The NeuroCore system is built on a tri-material stack consisting of silicon photonics (SiPh), silicon nitride (SiN), and indium phosphide (InP). Each material serves a specific role, chosen for performance and manufacturability.The light source originates from an InP laser diode. InP is the only one of the three with a direct bandgap, making it ideal for efficient light generation. The laser couples into the waveguide mesh through an optimized interface designed to minimize insertion loss.From there, the light enters the heart of the system: a configurable mesh built from SiN and SiPh waveguides and couplers. The SiN component is critical for maintaining signal strength. Its ultra-low propagation loss enables long path lengths without degrading optical power, essential when light must pass through dozens or hundreds of interferometers.The SiPh layer brings dynamic functionality. Silicon’s electro-optic properties enable phase shifting via electrical signals, allowing network weights to be programmed and updated in real-time. Phase shifters on each MZI arm allow real-time reconfiguration of the optical matrix.At the output, integrated photodiodes convert the optical signals back into electrical form. This stage closes the loop, feeding processed data into external systems or storage. Alongside the mesh are control electronics, including drivers, calibration feedback systems, thermal stabilizers, and readout modules, that ensure consistent and accurate behavior under real-world conditions.<img src="https://s3-us-west-1.amazonaws.com/wevolver-project-images/froala%2F1753121809135-flow+chart.jpg" style="width: 100%px;" class="fr-fic fr-dib">System Design - Flowchart and/or Block Diagram | Source: NeuroCore Photonic Integrated Neuron Chip Submission&nbsp;In short, it’s a complete optical MAC engine, backed by precision electrical tuning, modular, programmable, and ready to scale.<h2>Applications in AI, ML, and High-Performance Systems</h2>The immediate applications for this technology are in environments where AI inference needs to be fast, power-efficient, and scalable. Data centres are the obvious starting point. By offloading key layers of a deep neural network to photonic meshes, server clusters can reduce heat output and energy draw without compromising throughput.Edge AI is another compelling use case. In self-driving cars, for example, photonic inference engines can process lidar or camera data in real-time without overheating the system or draining the battery. Similarly, in medical diagnostics, where speed and accuracy are crucial, optical neural networks could enable faster and more responsive cancer detection tools.Photonic acceleration also aligns with broader sustainability goals. As AI becomes a baseline utility, the energy costs of computation matter more than ever. Reducing per-inference energy use at scale could significantly decrease the carbon footprint of machine learning.And because the design is modular, the system can scale with model size. Larger networks can be mapped to larger meshes. Photonic layers can be stacked or tiled. Unlike traditional chip designs, this mesh doesn’t require rethinking the architecture with every increase in model parameter count.<h2>Feasibility and Roadmap Ahead</h2>NeuroCore’s project is currently in its research and planning phase. The team has completed a rigorous evaluation of photonic neural network design principles, material compatibility, and system architecture. The focus is now on simulation: modelling mesh behaviour, optimizing phase control circuits, and evaluating insertion losses across key paths.One of the early challenges is the fabrication process. Integrating SiN, SiPh, and InP on a single chip requires precise alignment and bonding techniques to ensure optimal performance. This hybrid integration is achievable but demands advanced packaging workflows. Another challenge is stability. Optical systems are sensitive to temperature variations, so maintaining phase coherence requires real-time feedback and thermal compensation.Fortunately, ecosystems like PhotonDelta are built to accelerate this kind of development. Access to fabrication pipelines, design support, and industry mentoring will be crucial in transforming NeuroCore’s early-stage design into a functional prototype. With the right partnerships, the accelerator could transition from concept to chip far quicker than most standalone efforts.<h2>Conclusion: Lighting the Path to Scalable AI</h2>AI isn’t slowing down, but our current hardware might. As neural networks grow deeper and data volumes balloon, the pressure on electrical systems to keep pace is becoming unsustainable. Photonic computing is becoming a necessity, not an alternative.NeuroCore’s submission to the PhotonDelta Global Photonics Engineering Contest outlines a compelling future: scalable, energy-efficient, high-speed AI acceleration built on the principles of light physics. The designed hybrid photonic chip reimagines how and where computation happens.As AI capabilities expand, the supporting infrastructure must also evolve. Innovations like this suggest that the future of artificial intelligence may rely not only on traditional silicon, but also on the integration of photonic technologies.

Semiconductor architecture

ORGANIZATIONS.

SHAPING THE INDUSTRY.

Arm

ROHM Semiconductor

Latest Posts

Fully Depleted Silicon on Insulator (FDSOI) Theory, Design and Applications for Modern Engineers

Designing in Milliwatts: Rethinking Compute Architecture with the Electron E1 Processor

How Integrated Photonics Could Redefine Machine Learning Efficiency