Traditionally, the chip side of hardware design has been a closed profession. Today, the barrier to entry has been considerably lowered and people from startup-aligned engineers to students and even hobbyists are able to design processors. This leads to the question of ASIC vs FPGA, and whether it’s better to build a physical silicon chip or implement a design in “gateware” on configurable silicon.

Whether you’re considering an accelerator with a custom design tailored for a specific workload, a digital-signal processor (DSP), a real-time microcontroller, a high-performance microprocessor, or you’re simply looking to experiment, it's a question which requires careful consideration.

What is an FPGA?

An FPGA is a field-programmable gate array (FPGA), a chip with functions that have not been set in stone — or, rather, silicon. An FPGA can be reprogrammed at will using “gateware” which uses programmable interconnects to link the chip's internal configurable logic blocks (CLBs) in a way which redefines its capabilities. If you've designed a chip's schematic or have an algorithm in software, you can likely create a gateware version for an FPGA.

FPGAs aren’t the only type of reconfigurable hardware. A complex programmable logic device (CPLD) offers similar customizability, designed as a successor to the Programmable Array Logic (PAL) chips which preceded them, and is likewise reprogrammable at will. The two are often used together. CPLDs have features, like the ability to operate with a minimum of peripheral devices, which make them a handy way to extend an FPGA design.

The key for both FPGAs and CPLDs is that they’re a blank slate. You are given the task of defining what the chip should do. If you change your mind you can modify the design at any time, or even replace it with something entirely different. This makes an FPGA extremely cost effective for prototyping and experimentation while helping to reduce time-to-market for small-scale production runs.

What is an ASIC?

An ASIC is an application-specific integrated circuit (ASIC), meaning a packaged semiconductor with a fixed purpose matched to a formal specification. Exactly what the purpose is depends on its design. An ASIC may be used to decode a radio signal, or to control a motor, or even drive a smartphone or games console. Having only the resources it needs, and being tailored to a given task, means that it can operate at a high speed and more efficiently than a general-purpose processor or FPGA.

The key differentiation in ASIC vs FPGA is that an ASIC is finalized at the foundry, where transistors and other components are placed, and cannot be changed once manufactured. If its purpose is retired or needs to be updated, the ASIC needs to be recycled and replaced with a newly-manufactured version. This stands in stark contrast with an FPGA, which can simply be provided with new gateware.

There are numerous reasons why ASICs, and not FPGAs, are the prevalent component in modern high volume electronic devices, though. The question of ASIC vs FPGA is less clear-cut than it might at first seem.

Design Flow

While early chip design involved drafting tables, set-squares, pens, and sticky tape — the latter living on in the terminology “tape-out,” when a design is laid out ready for manufacturing — the modern design flow for both ASICs and FPGAs is similar.

In either case, a design is put together using a hardware description language (HDL) like Verilog or VHDL. The designer is effectively writing a program, but rather than software the result is instructions on how either a physical ASIC or the gateware of an FPGA should operate. Electronic design automation tools (EDA tools) are likewise available for both, providing a route to synthesis of an FPGA design or a tape-out for ASIC production.

During the design process there’s the requirement for testing. Here, ASICs and FPGAs begin to diverge: While both ASIC and FPGA HDL designs can be tested using simulation and formal verification, the FPGA design can be loaded onto an actual FPGA and tested in-circuit. The ASIC design, however, can only be committed to hardware as part of an expensive production run.

Many ASIC designs — or, for more complex designs, sub-sections thereof — begin life as FPGA designs. Once tested in-circuit using an FPGA, the design is modified for production and sent to a fabrication facility for production as an ASIC. As a result, in many cases, it’s less a question of “ASIC vs FPGA” and more “ASIC and FPGA.”

Performance and Efficiency

Despite their flexibility, FPGAs aren’t magic. In order to offer high configurability, they require numerous resources internally. As a result, an HDL design loaded onto an FPGA will always require a larger and slower chip than the same design produced as an ASIC at an equivalent technology level. The ASIC can be specifically tailored to the task and hold only the resources required for that particular design, with no wastage.

For the question of ASIC vs FPGA, this would seem to be a clear win for ASIC. Indeed, that’s one of the key reasons why ASICs massively outnumber FPGAs in production devices, particularly at high volume scales.

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It’s not a complete win for ASICs, though. If the choice is between an ASIC which has not been specifically tailored to a particular workload or an FPGA design which has gone through optimization, it’s entirely possible for the FPGA to outperform the ASIC. This can be seen where FPGAs are increasingly being used as high-performance accelerators for specific workloads alongside general-purpose chips like CPUs and GPUs.

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Power Consumption

Larger chips mean more power, and it’s here that the difference in ASIC vs FPGA really shows. Owing to their extremely generalized nature FPGAs are traditionally power-hungry devices. An ASIC, built on a modern technology platform, can draw such little power that it’s even possible to drive a project using solely harvested energy.

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Again, it’s a question of exactly what you’re comparing against. If you have a design where power consumption is key, the ASIC implementation will always be lower power than the FPGA implementation. If your choice is between running a workload on a general-purpose processor or an FPGA with gateware tailored to that specific task, it’s entirely possible for the FPGA to run faster while simultaneously drawing less power.

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FPGAs are steadily becoming more power-efficient, too. While they’ll never come close to an equivalent ASIC, some modern FPGA devices like Microchip’s PolarFire and mixed-function PolarFire SoC (System on Chip) ranges are designed for power efficiency. In many cases they can replace older-generation ASICs while requiring less power.

Configuration

The configuration of an FPGA happens in the gateware, as generated from the HDL program written by the chip designer. It’s flexible, and providing the FPGA has sufficient resources can be extended, shrunk, tweaked, or replaced. It does, however, rely on external components for bootstrapping, which is where a CPLD can assist.

An ASIC’s configuration is entirely fixed once manufactured. While minor changes can be made using software workarounds or microcode updates, there’s no way to completely change the operation of the chip without physically replacing it.

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It’s this inflexibility which has driven a reconsideration of the ASIC vs FPGA question, and increasing interest in combining the best of both worlds. Many larger ASIC designs now include embedded FPGA (eFPGA) capabilities. FPGAs have also become available which integrate ASIC components including general-purpose processors, so as to reduce the need for external hardware.

Barrier to Entry

If this article had been written just a few years ago, the question of barrier to entry would have been a clear win for the FPGA. Producing physical ASICs is an undeniably complex undertaking and the software for it was often guarded behind high-priced licenses. Even then, once your HDL design had been tested in simulation, actually producing it would require considerable investment.

Today, though, things are different. The rise of the free and open source silicon (FOSSi) movement has dramatically lowered the barrier to entry. Just as FPGA designers have long had the option of using fully-open toolchains, as promoted by organizations including the OSFPGA Foundation, now ASIC designers can get started at zero cost. Educational programs like Matthew Venn’s Zero to ASIC course offer an easily-approached introduction.

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For now it’s still easier to get started with FPGAs than ASIC designs, particularly for absolute beginners. A broader range of companies offer FPGA resources, from hardware to training, and toolchains are both well supported and heavily documented.

Analog blocks

There’s one key area where ASICs and FPGAs diverge dramatically: Analog support. FPGAs are primarily digital devices, concerned with digital logic, but not all electronics are digital.

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The majority of FPGAs available today are purely digital devices, offering any analog support as fixed-functional peripherals. While there is an equivalent for analog electronics, the field-programmable analog array (FPAA), they’re not commonly seen.

An ASIC, by contrast, can be manufactured using any physically-possible components including analog, digital, or a mixture of both. Where projects intrude on the analog domain, an ASIC will likely prove the only choice. Alternatively, a split design can be used with an FPGA taking care of the digital side and an ASIC or discrete off-the-shelf components handling analog work.

Cost

The biggest decider when looking at ASIC vs FPGA is cost. For prototyping and even small-scale production, there’s no question that FPGA wins out. Fully-functional FPGA hardware can be purchased for mere dollars, and the supporting software is usually provided free of charge for individuals and startups.

ASIC companies, by contrast, have typically locked their  process design kits (PDKs) behind expensive licenses or guaranteed minimum order quantities in the tens or hundreds of thousands. As a result, the non-recurring engineering cost (NRE cost) for ASIC design has been considerably higher than for FPGA work.

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That’s changing. Google’s open-source division recently partnered with chip fab Skywater Technologies and ASIC design specialist Efabless to launch the Open MPW Shuttle program. The program lets anyone access a process design kit and a production slot to have physical ASICs built at zero cost, providing the design is released under an open-source license. For closed-source commercial designs, Efabless offers the alternative chipIgnite program which brings the cost to produce up to 300 ASICs to under $10,000. While far from cheap, it represents a unit cost a fraction of what it would have been just a few years ago.

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If you’re scaling to production, though, there’s no question as to the winner in the ASIC vs FPGA argument: When you’re producing chips in the thousands, an ASIC implementation will always cost less per-chip than the equivalent design implemented in gateware on an FPGA. The more chips you produce the bigger that gap gets, which is the reason it’s rare to see volume production of devices with FPGAs.

Conclusion

There are plenty of reasons to choose to work towards implementing a chip design on an FPGA instead of an ASIC. For small-scale efforts that may well be the only choice — for now, at least. There are just as many reasons to aim for an ASIC implementation, however. This is particularly true where performance and power draw are more important than unit cost, or when a project scales into mass production.

Taking the question of ASIC vs FPGA as a binary, however, is largely missing the point. The technologies are complementary, and as increasing volumes of ASICs ship with eFPGA components and FPGAs begin to increase their bundled ASIC blocks it’s going to become increasingly difficult to draw a line between the two.

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Growing interest in free and open-source silicon is going to continue to push innovation for both FPGA and ASIC development, and will continue to drop the barriers to entry, too. If you’ve never before considered delving into the world of ASICs and FPGAs, there has never been a better time.