Thin film deposition is a process used to create thin film coatings on different materials. Thin films can consist of metal, semiconductors, and dielectrics, providing them with different properties. These properties translate to benefits such as electrical insulation, optical transmission, and corrosion resistance, that can be used to improve substrate performance. This article explores the processes of thin film deposition, along with its types, parameters, benefits, drawbacks, and applications.

Thin Film Deposition: Everything You Need to Know

Smart connected devices are being deployed in all industries, but the one that could have the greatest impact for individuals is within healthcare. In this article we will take a deep dive into the <a href="https://www.renesas.com/eu/en/application/iot-applications/smart-health/smart-connected-pulse-oximeter" rel="noopener noreferrer" target="_blank">smart connected pulse oximeter</a>, which is a super-low power system that can accurately measure blood oxygen levels in patients. We will take a look at the system&rsquo;s components, the unique features of the design, and why this solution is just the beginning in a bright future for smart medical devices.<h2>What is a pulse oximeter?</h2>A pulse oximeter measures the oxygen saturation of the blood in order to determine how well the heart is pumping oxygenated blood to the furthest extremities, such as the arms and legs [1]. Common devices clip a probe onto the patient&rsquo;s ear or fingertip to measure blood oxygen levels. Traditionally, these devices were attached to a monitor directly, or are often seen as part of a blood pressure machine in doctor&rsquo;s offices and hospitals.&nbsp;Healthcare professionals use oximeters quite frequently. They can be used to monitor a patient&rsquo;s current condition if they are suspected of having or diagnosed with a heart attack, heart failure, anemia, lung cancer, asthma, or pneumonia. In addition, patients that have undergone surgery that required sedation or are being subjected to a stress test to assess their cardiovascular abilities will also be monitored using a pulse oximeter&nbsp;[1]. The data captured by the oximeter provides crucial feedback to doctors, nurses, and technicians, which can help treat and monitor patients every day.During the COVID-19 pandemic, doctors began using at-home pulse oximeters to monitor blood oxygen levels of high-risk patients with the virus, such as those with diabetes, those who were pregnant, those with chronic illnesses, and those who were elderly. By taking readings on the portable sensor twice a day, patients were asked to let their doctor know if the reading dropped below 95%. If at any point a patient&rsquo;s blood oxygen level dropped to 90% or lower, they were told to seek immediate attention and to get to the emergency department. Early detection of lower blood saturation limits led to better outcomes in patients who used a pulse oximeter. A study in South Africa determined that a 50% reduction in patient mortality was possible if pulse oximeters were used to get patients the care they required as soon as blood oxygen levels dropped [2]. &nbsp;&nbsp;<h2 dir="ltr">Case Study: Renesas Smart Oximeter design</h2>To bring smart wireless technology to a commonly used medical tool, <a href="https://www.renesas.com/eu/en/application/iot-applications/smart-health/smart-connected-pulse-oximeter" rel="noopener noreferrer" target="_blank">Renesas developed the Smart Connected Pulse Oximeter.&nbsp;</a>Improving on traditional wired probes, the Smart Connected Pulse Oximeter uses a super-low power Bluetooth&reg; Low Energy (LE) System-on-Chip to relay the data to a smartphone app. The company has developed both iOS and Android applications that patients can download for free, and the software itself is open source for the reference design, allowing for future app improvements and collaborations within the industry.&nbsp;For example, healthcare practitioners could work together with app developers to create an interface that would serve their patient population and their own record-keeping needs. Doctors would have the best idea of how tech-savvy their patient population is and how simple the user interface would need to be. Bluetooth&reg; connection, for instance, may need to be automatic, or there may need to be tutorials in place for patients. In addition, doctors would be able to help direct the ideal frequency of checks per day and work with developers to add in notifications for the patient, so they don&rsquo;t forget to check their blood oxygen saturation. Because the device records the levels in the app, it could be further developed to connect to servers that the doctor has access to in order to help monitor the patient.&nbsp;The Smart Oximeter by Renesas is powered by two AAA batteries on the back of the board. Patients connect their smartphone to the oximeter using the Bluetooth&reg; module and can then rest their fingertip on an OB1203 biosensor. The biosensor on the chip is the smallest available at 4.2mm x 2 mm x 1.2 mm. A red light can be seen under the fingertip while measurements are taken, including heart rate, blood oxygen concentration, profusion index, and battery level, which show up in the smartphone application. Measurements take approximately six seconds, and through the use of a medical-grad algorithm have been shown to be accurate on even the most difficult-to-measure patients.Previously, pulse oximeters were not wireless devices that could connect to smartphones. They were small devices that patients used to measure their blood oxygen levels at home. But with advances in&nbsp;Bluetooth&reg; technology, including the size of the chip and the minimal energy it consumes, the pulse oximeter can now be brought online. Currently, this allows for a small device to be used at home, and it allows for greater accuracy in readings helping more patients get to the hospital if their blood oxygen levels get too low. Adding the&nbsp;Bluetooth&reg; capability also opens the door to remote monitoring both by healthcare practitioners and loved ones who are keeping track of their friends&rsquo; and family&rsquo;s health. The data can now be transmitted to the caretaker&rsquo;s phone.<img src="https://images.wevolver.com/eyJidWNrZXQiOiJ3ZXZvbHZlci1wcm9qZWN0LWltYWdlcyIsImtleSI6ImZyb2FsYS8xNjgyNTA0Mzg1MDU2LXB1bHNlIDEucG5nIiwiZWRpdHMiOnsicmVzaXplIjp7IndpZHRoIjo5NTAsImZpdCI6ImNvdmVyIn19fQ==" style="width: 300px;" class="fr-fic fr-dib">Layout of the system. Image credit; Renesas<h2 dir="ltr">Benefits of the Smart Oximeter for the healthcare industry and end consumers</h2>The Smart Oximeter with the available mobile applications is a complete solution available to different healthcare providers. While hospital departments and doctor&rsquo;s offices may have traditional wired oximeters in place, they can be bulky and cumbersome to move from room to room. The Smart Oximeter offers a compact and portable solution for healthcare professionals, and those who are providing their services in patient&rsquo;s homes. They can easily transport the Smart Oximeter on their person and can rest assured it will be using the very little battery energy throughout the day.Because of the lightweight design and mobile monitoring characteristics, the Smart Oximeter could also be used on gym or physiotherapy equipment, like treadmills, ellipticals, and stationary bikes. Patients would be able to monitor their blood oxygen levels, and healthcare providers could receive the data from their patients even between appointments.&nbsp;As a wearable device, patients can rest assured that they can check if their blood oxygen saturation is sufficient or not. This will also ensure patients get to their doctor or local emergency department when blood oxygen levels are too low. The simplicity of the Smart Oximeter by Renesas means it can be used in multiple settings to assist the maximum number of people afflicted with conditions or undergoing treatments and surgeries that may lower their blood oxygen saturation.<h2 dir="ltr">Expanding IoT and smart healthcare solutions to save lives</h2>While engineers have been expanding the Internet of Things (IoT) into all technical realms, the most common examples that seem to be at the forefront are those in manufacturing or smart home systems or even industrial energy applications. But by taking health monitors, sensors, and the latest wireless technology into the IoT domain, many people will benefit from the advances, and not just select high-tech industries.&nbsp;A simple, but powerful, device like the oximeter could be made readily available to patients and their healthcare professionals to more effectively monitor them. For example, if a patient sees their specialist once every two weeks to have their blood oxygen saturation measured, there is a large time lapse within which the patient may decline. Putting the Smart Oximeter into the hands of healthcare frontline professionals and patients could truly save many lives. And with the adoption of smart mobile monitoring, the industry and patients will grow more comfortable of the technology and the elevated level of monitoring and care they will have access to, resulting in many more smart applications in the years to come.&nbsp;<h2 dir="ltr" id="isPasted">Summary</h2>The Renesas Smart Oximeter is a complete solution to monitoring a patient&rsquo;s blood oxygen saturation wirelessly. Powered by two AAA batteries on the back of the chip, the Renesas Smart Oximeter uses a super-low power Bluetooth&reg; System-on-Chip to connect to a smartphone app where the heart rate, blood oxygen concentration, profusion index, and battery levels are displayed. The biosensor on the chip is the smallest available at just 4.2 mm x 2 mm x 1.2 mm, where a patient rests their fingertip.&nbsp;By bringing a smart mobile solution to the healthcare industry, Renesas has made the oximeter more portable, more energy efficient, and more accurate than traditional oximeters. If deployed to healthcare practitioners and their patients more widely, monitoring accuracy and frequency would increase to ensure adequate patient blood oxygen levels, meaning the Renesas Smart Oximeter could literally save lives. &nbsp;&nbsp;<h2 dir="ltr">References:</h2>[1] Johns Hopkins Medicine. Pulse Oximetry [Internet]. Maryland: The Johns Hopkins University; 2022 [cited 2022 May 12]. Available from: <a href="https://www.hopkinsmedicine.org/health/treatment-tests-and-therapies/pulse-oximetry" rel="noopener noreferrer" target="_blank">https://www.hopkinsmedicine.org/health/treatment-tests-and-therapies/pulse-oximetry</a>[2] Parker-Pope, Tara. Do I Still Need a Pulse Oximeter? A new study shows just how lifesaving home monitoring of oxygen levels can be. [Internet]. New York: The New York Times; 2021 [cited 2022 May 15]. Available from: <a href="https://www.nytimes.com/2021/10/05/well/live/covid-pulse-oximeter.html" rel="noopener noreferrer" target="_blank">https://www.nytimes.com/2021/10/05/well/live/covid-pulse-oximeter.html</a>

A life-saving application of a super-low power system. 


Simply saving lives: A deep look at the simple but brilliant pulse oximeter

This article was first published on <a href="https://news.mit.edu/2023/new-chip-mobile-devices-knocks-out-unwanted-signals-0221" id="isPasted" rel="noopener noreferrer" target="_blank">MIT News</a>. &nbsp; &nbsp;<hr>Imagine sitting in a packed stadium for a pivotal football game &mdash; tens of thousands of people are using mobile phones at the same time, perhaps video chatting with friends or posting photos on social media. The radio frequency signals being sent and received by all these devices could cause interference, which slows device performance and drains batteries.Designing devices that can efficiently block unwanted signals is no easy task, especially as 5G networks become more universal and future generations of wireless communication systems are developed. Conventional techniques utilize many filters to block a range of signals, but filters are bulky, expensive, and drive up production costs.MIT researchers have developed a circuit architecture that targets and blocks unwanted signals at a receiver&rsquo;s input without hurting its performance. They borrowed a technique from digital signal processing and used a few tricks that enable it to work effectively in a radio frequency system across a wide frequency range.Their receiver blocked even high-power unwanted signals without introducing more noise, or inaccuracies, into the signal processing operations. The chip, which performed about 40 times better than other wideband receivers at blocking a special type of interference, does not require any additional hardware or circuitry. This would make the chip easier to manufacture at scale.&ldquo;We are interested in developing electronic circuits and systems that meet the demands of 5G and future generations of wireless communication systems. In designing our circuits, we look for inspirations from other domains, such as digital signal processing and applied electromagnetics. We believe in circuit elegance and simplicity and try to come up with multifunctional hardware that doesn&rsquo;t require additional power and chip area,&rdquo; says senior author Negar Reiskarimian, the X-Window Consortium Career Development Assistant Professor in the Department of Electrical Engineering and Computer Science (EECS) and a core faculty member of the Microsystems Technology Laboratories.Reiskarimian wrote the paper with EECS graduate students Soroush Araei, who is the lead author, and Shahabeddin Mohin. The work is being presented at the International Solid-States Circuits Conference.<h2>Harmonic interference</h2>The researchers developed the receiver chip using what is known as a mixer-first architecture. This means that when a radio frequency signal is received by the device, it is immediately converted to a lower-frequency signal before being passed on to the analog-to-digital converter to extract the digital bits that it is carrying. This approach enables the radio to cover a wide frequency range while filtering out interference located close to the operation frequency.While effective, mixer-first receivers are susceptible to a particular kind of interference known as harmonic interference. Harmonic interference comes from signals that have frequencies which are multiples of a device&rsquo;s operating frequency. For instance, if a device operates at 1 gigahertz, then signals at 2 gigahertz, 3 gigahertz, 5 gigahertz, etc., will cause harmonic interference. These harmonics can be indistinguishable from the original signal during the frequency conversion process.&nbsp; &nbsp;&nbsp;&ldquo;A lot of other wideband receivers don&rsquo;t do anything about the harmonics until it is time to see what the bits mean. They do it later in the chain, but this doesn&rsquo;t work well if you have high-power signals at the harmonic frequencies. Instead, we want to remove harmonics as soon as possible to avoid losing information,&rdquo; Araei says.To do this, the researchers were inspired by a concept from digital signal processing known as block digital filtering. They adapted this technique to the analog domain using capacitors, which hold electric charges. The capacitors are charged up at different times as the signal is received, then they are switched off so that charge can be held and used later for processing the data.&nbsp;&nbsp;These capacitors can be connected to each other in various ways, including connecting them in parallel, which enables the capacitors to exchange the stored charges. While this technique can target harmonic interference, the process results in significant signal loss. Stacking capacitors is another possibility, but this method alone is not enough to provide harmonic resilience.Most radio receivers already use switched-capacitor circuits to perform frequency conversion. This frequency conversion circuitry can be combined with block filtering to target harmonic interference.<h2>A precise arrangement</h2>The researchers found that arranging capacitors in a specific layout, by connecting some of them in series and then performing charge sharing, enabled the device to block harmonic interference without losing any information.&ldquo;People have used these techniques, charge sharing and capacitor stacking, separately before, but never together. We found that both techniques must be done simultaneously to get this benefit. Moreover, we have found out how to do this in a passive way within the mixer without using any additional hardware while maintaining signal integrity and keeping the costs down,&rdquo; he says.They tested the device by simultaneously sending a desired signal and harmonic interference. Their chip was able to block harmonic signals effectively with only a slight reduction in signal strength. It was able to handle signals that were 40 times more powerful than previous, state-of-the-art wideband receivers.<hr>&quot;Reprinted with permission of&nbsp;<a href="https://news.mit.edu/2023/new-chip-mobile-devices-knocks-out-unwanted-signals-0221" id="isPasted" rel="noopener noreferrer" target="_blank">MIT News</a>&quot; &nbsp;

MIT researchers have developed a receiver chip for a mobile device that targets and blocks unwanted radio frequency signals at the receiver’s input, without hurting its performance or slowing down the device. Credit: MIT News. Chip image courtesy of the researchers.

The receiver chip efficiently blocks signal interference that slows device performance and drains batteries.

New chip for mobile devices knocks out unwanted signals

AI has the potential to solve some of the world&rsquo;s most challenging problems. But the computational power needed to run the most advanced AI algorithms is rapidly exceeding the capabilities of today&rsquo;s computers.&ldquo;EnCharge AI is unlocking the incredible capability that artificial intelligence can deliver by providing a platform that can match its computing needs, and performing AI computations close to where the data in the real world is being generated,&rdquo; said company founder&nbsp;<a data-extlink="" href="https://ece.princeton.edu/people/naveen-verma" rel="noreferrer" target="_blank">Naveen Verma</a>, professor of electrical and computer engineering and director of the&nbsp;<a data-extlink="" href="https://kellercenter.princeton.edu/" rel="noreferrer" target="_blank">Keller Center for Innovation in Engineering Education</a> at Princeton University.Modern AI requires immense computing capability, and works by shipping data off to huge data centers in the cloud, where algorithms process the data and then send the results back to the user. But at the cutting edge of the field where the volume of data is immense, the transfer to and from the cloud can be very expensive, take too long, or not even be feasible, said Verma, who is also the director of Princeton&rsquo;s programs in <a data-extlink="" href="https://kellercenter.princeton.edu/certificates/program-entrepreneurship" rel="noreferrer" target="_blank">Entrepreneurship&nbsp;</a>and <a data-extlink="" href="https://kellercenter.princeton.edu/certificates/program-technology-society" rel="noreferrer" target="_blank">Technology and Society</a>.To skip the costly and time-consuming step of exchanging data with the cloud, the&nbsp;<a href="https://enchargeai.com/" target="_blank">EnCharge AI</a> team designed a new kind of computer chip that allows AI to run locally, directly on the device. But because these devices are much smaller in size compared to data centers in the cloud, they must run with much higher efficiency. That&rsquo;s where in-memory computing comes in.&ldquo;We find ourselves in a position where we&rsquo;re really rethinking the fundamentals of computing, from the basic devices to the overall architectures,&rdquo; Verma said. &ldquo;That&rsquo;s an exciting thing for researchers, and that&rsquo;s been a big focus for my group for many years.&rdquo;To achieve this, the EnCharge AI team designed their chip using highly precise circuits that can be considerably smaller and more energy-efficient than today&rsquo;s digital computing engines, allowing the circuits to be integrated within the chip&rsquo;s memory. This in-memory approach provides the high efficiency needed for modern AI-driven applications.&ldquo;EnCharge AI&rsquo;s technology, based on the work of Naveen and his graduate students, is truly innovative and potentially transformative in enabling widespread use of AI,&rdquo; said&nbsp;<a data-extlink="" href="https://ece.princeton.edu/people/andrea-goldsmith" rel="noreferrer" target="_blank">Andrea Goldsmith</a>, dean of the School of Engineering and Applied Science and Arthur LeGrand Doty Professor of Electrical and Computer Engineering and member of the advisory board for EnCharge AI.&ldquo;This has the potential to change the way we use computing in our daily lives,&rdquo; said Murat Ozatay, a former graduate student in Verma&rsquo;s lab and now a key engineer with EnCharge AI. &ldquo;Our ultimate goal is to build the best AI chip in terms of power efficiency and performance.&rdquo;Ozatay said that working on research that led to a startup has given him new perspective on how research can be impactful outside of the lab. &ldquo;I think seeing this kind of thing drives other students to want to build something new,&rdquo; he said.Verma said that some of the most exciting applications for their chip lie in automation, which involves taking complex physical tasks and automating them in a way that leverages or expands the capability of humans.The chip could cut costs and improve performance for robots in large-scale warehouses, in retail automation such as self-checkout, safety and security operations, and in drones for delivery and industrial purposes. The chips are programmable, capable of working with different types of AI algorithms, and scalable, enabling applications to grow in complexity.&ldquo;This is all possible through a user interface that&rsquo;s seamless,&rdquo; Verma said. &ldquo;For AI innovators, the chip fits into your life easily without disrupting your ability to innovate.&rdquo;&ldquo;This is a challenging field for investors and others in the innovation sphere to jump into and engage in. There are a range of technologies that try to break away from the limitations in ways conventional computers do things &mdash; you need to put in the research and work with folks to help them understand which technologies will and won&rsquo;t work, and why,&rdquo; Verma said, noting that the startup has raised $21.7 million from investors in its first round of financing.Verma said that universities play an important role in driving innovation in new and differentiated technologies. &ldquo;Through the deep research we can do at universities, we can rigorously build out these technologies to maturity, to move with solid footing towards real-world applications,&rdquo; Verma said. &ldquo;Of course, this requires that universities give faculty the time and flexibility to do this, in the way that Princeton has for me.&rdquo;Goldsmith, who is on Biden&rsquo;s&nbsp;<a data-extlink="" href="https://www.whitehouse.gov/pcast/#:~:text=President%20Biden's%20PCAST%20consists%20of,secretaries%2C%20and%20two%20Nobel%20laureates." rel="noreferrer" target="_blank">Presidential Council of Advisors for Science and Technology</a>, said that investing in the chip industry, including in hardware that enables advanced artificial intelligence, is essential for the United States to ensure its national security and economic prosperity.&ldquo;The U.S. government has underinvested in the chip industry for decades, leaving such investment to the private sector. As a result, we have lost our lead in some areas of hardware and semiconductors,&rdquo; Goldsmith said. &ldquo;The Chips and Science Act is a once-in-a-generation investment in hardware innovation and manufacturing, and those innovations will come from universities.&rdquo;Startups are one of several ways that university technologies can lead to societal benefit. To increase&nbsp;<a data-extlink="" href="https://innovation.princeton.edu/" rel="noreferrer" target="_blank">innovation impact</a>, Princeton helps researchers who wish to launch companies or non-profits by providing information about how to find funding, how to evaluate customer need for a product, and help with applying for patents.&ldquo;To be a successful entrepreneur, you need more than just funding,&rdquo; Goldsmith said. &ldquo;You need an ecosystem including investors and advisers to help transform research innovations into successful products around which a company can be built.&rdquo;As part of this support system, Princeton began the <a href="https://research.princeton.edu/news/princeton%E2%80%99s-technology-accelerator-fund-celebrates-10-years-fueling-innovations#:-:text=ip%20accelerator" target="_blank">Intellectual Property (IP) Accelerator Fund</a> program ten years ago to provide extra funding for researchers to further develop their early-stage innovations. Verma&rsquo;s research team received an IP Accelerator Fund award in 2019, which Verma said was critically enabling for the development of their technology.&ldquo;Providing funds to help faculty develop technologies is very important for the University,&rdquo; Goldsmith said. &ldquo;The cycle of taking the research that we do, maximizing its impact by putting it into practice, and in that process opening up new research areas and new methodologies of teaching maximizes the impact of the research that our faculty are doing.&rdquo;&ldquo;People think innovation is about starting companies, but it&rsquo;s not,&rdquo; Goldsmith said. &ldquo;It&rsquo;s really about creating new ideas and going down paths that have not been followed before.&rdquo;

Princeton researchers have developed a new kind of computer chip using highly precise circuits that can be integrated within the chip's memory, providing the high efficiency needed for modern artificial intelligence applications. Photo by Hongyang Jia/Princeton University

A startup based on Princeton research is rethinking the computer chip with a design that increases performance, efficiency and capability to match the computational needs of technologies that use artificial intelligence (AI). Using a technique called in-memory computing, the new design can store data and run computation all in the same place on the chip, drastically reducing cost, time and energy consumption in AI computations.

EnCharge AI reimagines computing to meet needs of cutting-edge AI

We see light and colours around us every day. However, to analyse the information it carries, we must analyse light using spectrometers, in the lab. These devices detect sparkles and substances that our eyes would otherwise not notice.Now, an international team of researchers, including the University of Cambridge, have designed a miniaturised spectrometer that breaks all current resolution records, and does so in a much smaller package, thanks to computational programmes and AI.The new miniaturised devices could be used in a broad range of sectors, from checking the quality of food to analysing starlight or detecting faint clues of life in outer space. The&nbsp;<a href="https://www.science.org/doi/10.1126/science.add8544" target="_blank">results</a> are reported in the journal Science.Traditionally, spectrometers rely on bulky components to filter and disperse light. Modern approaches simplify these components to shrink footprints, but still suffer from limited resolution and bandwidth. Additionally, traditional spectrometers are heavy and take up extraordinary amounts of space, which limits their applications in portable and mobile devices.To tackle these problems, and shrink the size of the system, researchers have coupled layered materials with artificial intelligence algorithms. The result is an all-in-one spectrometer thousands of times smaller than current commercial systems. At the same time, it offers performance comparable to benchtop systems. In other words, these new spectrometers will provide portable alternatives to uncover otherwise invisible information, without even going into the lab.&ldquo;We eliminate the need for detector arrays, dispersive components, and filters. It&rsquo;s an all-in-one, miniaturised device that could revolutionise this field,&rdquo; said Dr Hoon Hahn Yoon, from Aalto University in Finland, first author of the paper. This spectrometer-on-chip technology is expected to offer high performance and new usability across science and industry.The detector uses van der Waals heterostructures &ndash; a &lsquo;sandwich&rsquo; of different ingredients, including graphene, molybdenum disulfide, and tungsten diselenide. Different combinations of material components enable light detection beyond the visible spectrum, as far as the near-infrared region. This means the spectrometer detects more than just colour, enabling applications such as chemical analysis and night vision.&ldquo;We detect a continuum spectrum of light, opening a world of possibilities in a myriad of markets,&rdquo; said Dr Yoon. &ldquo;Exploring other material combinations could uncover further functionalities, including even broader hyperspectral detection and improved resolution.&rdquo;AI is a key aspect of these devices, commonly called &lsquo;computational&rsquo; spectrometers. This technology compensates for the inherent noise increase that inevitably occurs when the optical component is wholly removed.&ldquo;We were able to use mathematical algorithms to successfully reconstruct the signals and spectra, it&rsquo;s a profound and transformative technological leap,&rdquo; said lead author Professor Zhipei Sun, also from Aalto University, and a former member of Cambridge&rsquo;s Department of Engineering. &ldquo;The current design is just a proof-of-concept. More advanced algorithms, as well as different combinations of materials, could soon provide even better miniaturised spectrometers.&rdquo;Spectrometers are used for toxin detection in food and cosmetics, cancer imaging, and in spacecraft &ndash; including the James Webb Space Telescope. And they will soon become more common thanks to the development and advancement of technologies such as the Internet of Things and Industry 4.0.The detection of light &ndash; and the full analysis of spectroscopic information &ndash; has applications in sensing, surveillance, smart agriculture, and more. Among the most promising applications for miniaturised spectrometers are chemical and biochemical analysis, thanks to the capabilities of the devices to detect light in the infrared wavelength range.The new devices could be incorporated into instruments like drones, mobile phones, and lab-on-a-chip platforms, which can carry out several experiments in a single integrated circuit. The latter also opens up opportunities in healthcare. In this field, spectrometers and light-detectors are already key components of imaging and diagnostic systems &ndash; the new miniaturised devices could enable the simultaneous visualisation and detection of &lsquo;chemical fingerprints&rsquo;, leading to possibilities in the biomedical area.&ldquo;Our miniaturised spectrometers offer high spatial and spectral resolution at the micrometre and nanometre scales, which is particularly exciting for responsive bio-implants and innovative imaging techniques,&rdquo; said co-author&nbsp;<a href="http://www.eng.cam.ac.uk/profiles/th270" target="_blank">Professor Tawfique Hasan</a>, from the&nbsp;<a href="https://www.graphene.cam.ac.uk/" target="_blank">Cambridge Graphene Centre</a>.This technology has huge potential for scalability and integration, thanks to its compatibility with well-established industrial processes. It could open up the future for the next generation of smartphone cameras that evolve into hyperspectral cameras that conventional colour cameras cannot do. Researchers hope their contribution is a stepping stone towards the development of more advanced computational spectrometers, with record-breaking accuracy and resolution. This example, they say, is just the first of many.<hr>Reference: Hoon Hahn Yoon et al. &lsquo;<a href="https://www.science.org/doi/10.1126/science.add8544" target="_blank">Miniaturized Spectrometers with a Tunable van der Waals Junction</a>.&rsquo; Science (2022). DOI: 10.1126/science.add8544.This article first appeared on the University of Cambridge <a href="https://www.cam.ac.uk/research/news/artificial-intelligence-powers-record-breaking-all-in-one-miniature-spectrometers" target="_blank">website</a>. Written by Fernando Gomollon-Bel and edited by Sarah Collins.&nbsp;

Using Artificial Intelligence (AI) to replace optical and mechanical components, researchers have designed a tiny spectrometer that breaks all current resolution records.

Artificial intelligence powers record-breaking all-in-one miniature spectrometers

In this article, we look at how Super Low power Wi-Fi and Bluetooth LE enable smart locks to be more agile and reliable by demonstrating these features with a case study from Renesas. 


Super Low Power Wi-Fi and Bluetooth LE Unlock Smart Locks

Digital information is everywhere in the era of smart technology, where data is continuously generated by and communicated among cell phones, smart watches, cameras, smart speakers and other devices. Securing digital data on handheld devices requires massive amounts of energy, according to an interdisciplinary group of Penn State researchers, who warn that securing these devices from bad actors is becoming a greater concern than ever before. &nbsp;Led by Saptarshi Das, Penn State associate professor of engineering science and mechanics, researchers developed a smart hardware platform, or chip, to mitigate energy consumption while adding a layer of security. The researchers published their results on June 23 in <a href="https://www.nature.com/articles/s41467-022-31148-z" rel="noreferrer noopener" target="_blank">Nature Communications</a>.&nbsp;&ldquo;Information from our devices is currently stored in one location, the cloud, which is shared and stored in large servers,&rdquo; said Das, who also is affiliated with the Penn State School of Electrical Engineering and Computer Science, the Materials Research Institute and the College of Earth and Mineral Sciences&rsquo; Department of Materials Science and Engineering. &ldquo;The security strategies employed to store this information are extremely energy inefficient and are vulnerable to data breaches and hacking.&rdquo;&nbsp;Cloud encryption is a current mode of security that converts data into a code to prevent unauthorized access. Popular messaging system WhatsApp, for example, uses the method, theoretically ensuring only the devices involved in the chat can access private messages. However, in practice, cloud encryptions are vulnerable to data leaks and are frequent targets for adversaries, according to researchers.&nbsp;&ldquo;Although software-based security modules are powerful, there exists a multitude of challenges with them,&rdquo; said first author Akhil Dodda, a Penn State engineering science and mechanics doctoral student. &ldquo;We developed a cryptographic platform using a two-dimensional material to overcome these security limitations.&rdquo;&nbsp;<img src="https://s3-us-west-1.amazonaws.com/wevolver-project-images/froala%2F1658324200920-body-PSN.jpg" style="width: 765px;" class="fr-fic fr-dib">Saptarshi Das, left, Penn State associate professor of engineering, science and mechanics, and Akhil Dodda, a Penn State engineering science and mechanics doctoral student, published a paper in Nature Communications on a security method for handheld devices that won&#39;t drain the battery. &nbsp;Credit: Kelby Hochreither/Penn State. All Rights Reserved. Commonly used to make transistors used in cellphones, silicon would not work to build a transistor small enough to save on energy use, researchers said. Instead, they turned to 2D materials, specifically molybdenum disulfide (MoS2), which is less than one nanometer thick, to create a low-power cryptographic chip. Penn State collaborators Joan Redwing, distinguished professor of materials science and engineering and electrical engineering, and Nicholas Trainor, a doctoral student in materials science and engineering, worked together to synthesize the MoS2 needed to create the chip. &nbsp;The chip employs 320 MoS2 transistors that each have a sensing unit, a storage unit and a computing unit to encrypt the data. To test the strength of the encryption process, researchers used machine learning algorithms, which allowed them to study the output patterns and predict input information.&nbsp;&ldquo;We found that the advanced machine learning techniques couldn&rsquo;t decode the encrypted information, reinforcing the resilience of the encryption process against machine learning attacks,&rdquo; Das said. &ldquo;Without prior knowledge of the information channels and decoding variables, it is extremely difficult to decode the information.&rdquo;&nbsp;Additionally, the researchers said, the energy consumed in encrypting the information was significantly less than silicon-based security methods. The result was a low-power, all-in-one chip that could sense, store, compute and communicate information among connected devices &mdash; a potential solution for users who want added security but cannot afford to drain their handheld device batteries in day-to-day use.&nbsp;&ldquo;In the near future, we plan to reach out to federal agencies and private corporations who specialize in smart security to extend and expand the scope of our work,&rdquo; Das said.&nbsp;

Penn State materials science and engineering researchers used molybdenum disulfide, a 2D material, to create a low-power cryptographic chip less than one nanometer thick. Credit: Kelby Hochreither/Penn State. All Rights Reserved.

Led by Saptarshi Das, Penn State associate professor of engineering science and mechanics, researchers developed a smart hardware platform, or chip, to mitigate energy consumption while adding a layer of security.

Smart chip senses, stores, computes and secures data in one low-power platform

This article was first published on <a href="https://news.mit.edu/2022/stackable-artificial-intelligence-chip-0613" id="isPasted" rel="noopener noreferrer" target="_blank">MIT News</a>. &nbsp;<hr>Imagine a more sustainable future, where cellphones, smartwatches, and other wearable devices don&rsquo;t have to be shelved or discarded for a newer model. Instead, they could be upgraded with the latest sensors and processors that would snap onto a device&rsquo;s internal chip &mdash; like LEGO bricks incorporated into an existing build. Such reconfigurable chipware could keep devices up to date while reducing our electronic waste.&nbsp;Now MIT engineers have taken a step toward that modular vision with a LEGO-like design for a stackable, reconfigurable artificial intelligence chip.The design comprises alternating layers of sensing and processing elements, along with light-emitting diodes (LED) that allow for the chip&rsquo;s layers to communicate optically. Other modular chip designs employ conventional wiring to relay signals between layers. Such intricate connections are difficult if not impossible to sever and rewire, making such stackable designs not reconfigurable.The MIT design uses light, rather than physical wires, to transmit information through the chip. The chip can therefore be reconfigured, with layers that can be swapped out or stacked on, for instance to add new sensors or updated processors.&ldquo;You can add as many computing layers and sensors as you want, such as for light, pressure, and even smell,&rdquo; says MIT postdoc Jihoon Kang. &ldquo;We call this a LEGO-like reconfigurable AI chip because it has unlimited expandability depending on the combination of layers.&rdquo;The researchers are eager to apply the design to edge computing devices &mdash; self-sufficient sensors and other electronics that work independently from any central or distributed resources such as supercomputers or cloud-based computing.&ldquo;As we enter the era of the internet of things based on sensor networks, demand for multifunctioning edge-computing devices will expand dramatically,&rdquo; says Jeehwan Kim, associate professor of mechanical engineering at MIT. &ldquo;Our proposed hardware architecture will provide high versatility of edge computing in the future.&rdquo;The team&rsquo;s results are published today in&nbsp;Nature Electronics. In addition to Kim and Kang, MIT authors include co-first authors Chanyeol Choi, Hyunseok Kim, and Min-Kyu Song, and contributing authors Hanwool Yeon, Celesta Chang, Jun Min Suh, Jiho Shin, Kuangye Lu, Bo-In Park, Yeongin Kim, Han Eol Lee, Doyoon Lee, Subeen Pang, Sang-Hoon Bae, Hun S. Kum, and Peng Lin, along with collaborators from Harvard University, Tsinghua University, Zhejiang University, and elsewhere.<h2>Lighting the way</h2>The team&rsquo;s design is currently configured to carry out basic image-recognition tasks. It does so via a layering of image sensors, LEDs, and processors made from artificial synapses &mdash; arrays of memory resistors, or &ldquo;memristors,&rdquo; that the team&nbsp;<a href="https://news.mit.edu/2020/thousands-artificial-brain-synapses-single-chip-0608" target="_blank">previously developed</a>, which together function as a physical neural network, or &ldquo;brain-on-a-chip.&rdquo; Each array can be trained to process and classify signals directly on a chip, without the need for external software or an Internet connection.In their new chip design, the researchers paired image sensors with artificial synapse arrays, each of which they trained to recognize certain letters &mdash; in this case, M, I, and T. While a conventional approach would be to relay a sensor&rsquo;s signals to a processor via physical wires, the team instead fabricated an optical system between each sensor and artificial synapse array to enable communication between the layers, without requiring a physical connection.&nbsp;&ldquo;Other chips are physically wired through metal, which makes them hard to rewire and redesign, so you&rsquo;d need to make a new chip if you wanted to add any new function,&rdquo; says MIT postdoc Hyunseok Kim. &ldquo;We replaced that physical wire connection with an optical communication system, which gives us the freedom to stack and add chips the way we want.&rdquo;The team&rsquo;s optical communication system consists of paired photodetectors and LEDs, each patterned with tiny pixels. Photodetectors constitute an image sensor for receiving data, and LEDs to transmit data to the next layer. As a signal (for instance an image of a letter) reaches the image sensor, the image&rsquo;s light pattern encodes a certain configuration of LED pixels, which in turn stimulates another layer of photodetectors, along with an artificial synapse array, which classifies the signal based on the pattern and strength of the incoming LED light.<h2>Stacking up</h2>The team fabricated a single chip, with a computing core measuring about 4 square millimeters, or about the size of a piece of confetti. The chip is stacked with three image recognition &ldquo;blocks,&rdquo; each comprising an image sensor, optical communication layer, and artificial synapse array for classifying one of three letters, M, I, or T. They then shone a pixellated image of random letters onto the chip and measured the electrical current that each neural network array produced in response. (The larger the current, the larger the chance that the image is indeed the letter that the particular array is trained to recognize.)The team found that the chip correctly classified clear images of each letter, but it was less able to distinguish between blurry images, for instance between I and T. However, the researchers were able to quickly swap out the chip&rsquo;s processing layer for a better &ldquo;denoising&rdquo; processor, and found the chip then accurately identified the images.&ldquo;We showed stackability, replaceability, and the ability to insert a new function into the chip,&rdquo; notes MIT postdoc Min-Kyu Song.The researchers plan to add more sensing and processing capabilities to the chip, and they envision the applications to be boundless.&ldquo;We can add layers to a cellphone&rsquo;s camera so it could recognize more complex images, or makes these into healthcare monitors that can be embedded in wearable electronic skin,&rdquo; offers Choi, who along with Kim previously developed a&nbsp;<a href="https://news.mit.edu/2021/smart-skin-vitals-0630" target="_blank">&ldquo;smart&rdquo; skin</a> for monitoring vital signs.Another idea, he adds, is for modular chips, built into electronics, that consumers can choose to build up with the latest sensor and processor &ldquo;bricks.&rdquo;&ldquo;We can make a general chip platform, and each layer could be sold separately like a video game,&rdquo; Jeehwan Kim says. &ldquo;We could make different types of neural networks, like for image or voice recognition, and let the customer choose what they want, and add to an existing chip like a LEGO.&rdquo;<hr>&quot;Reprinted with permission of&nbsp;<a href="https://news.mit.edu/2022/stackable-artificial-intelligence-chip-0613" id="isPasted" rel="noopener noreferrer" target="_blank">MIT News</a>&quot;&nbsp;

MIT engineers have created a reconfigurable AI chip that comprises alternating layers of sensing and processing elements that can communicate with each other. Credit: Figure courtesy of the researchers and edited by MIT News

The new design is stackable and reconfigurable, for swapping out and building on existing sensors and neural network processors.

Engineers build LEGO-like artificial intelligence chip

Traditionally, the chip side of&nbsp;hardware design&nbsp;has been a closed profession. Today, the barrier to entry has been considerably lowered and people from startup-aligned engineers to students and even hobbyists are able to design processors. This leads to the question of&nbsp;ASIC vs FPGA, and whether it&rsquo;s better to build a physical silicon chip or implement a design in &ldquo;gateware&rdquo; on configurable silicon.Whether you&rsquo;re considering an accelerator with a&nbsp;custom design&nbsp;tailored for a specific workload, a digital-signal processor (DSP), a real-time&nbsp;microcontroller, a&nbsp;high-performance&nbsp;microprocessor, or you&rsquo;re simply looking to experiment, it&#39;s a question which requires careful consideration.<h1 dir="ltr">What is an&nbsp;FPGA?</h1>An&nbsp;FPGA&nbsp;is a&nbsp;field-programmable gate array&nbsp;(FPGA), a chip with functions that have not been set in stone &mdash; or, rather, silicon. An&nbsp;FPGA&nbsp;can be reprogrammed at will using &ldquo;gateware&rdquo; which uses&nbsp;programmable interconnects&nbsp;to link the chip&#39;s internal&nbsp;configurable logic blocks&nbsp;(CLBs) in a way which redefines its capabilities. If you&#39;ve designed a chip&#39;s&nbsp;schematic&nbsp;or have an&nbsp;algorithm&nbsp;in software, you can likely create a gateware version for an&nbsp;FPGA.<img src="https://images.wevolver.com/eyJidWNrZXQiOiJ3ZXZvbHZlci1wcm9qZWN0LWltYWdlcyIsImtleSI6ImZyb2FsYS8xNjU1MTI4MTA0MjE0LWltYWdlMS5qcGciLCJlZGl0cyI6eyJyZXNpemUiOnsid2lkdGgiOjk1MCwiZml0IjoiY292ZXIifX19" style="width: 300px;" class="fr-fic fr-dib" alt="A picture of a Microchip PolarFire SoC system-on-chip, taken at an angle. The chip is marked as an engineering sample.">FPGAs&nbsp;aren&rsquo;t the only type of&nbsp;reconfigurable&nbsp;hardware. A complex programmable logic device (CPLD) offers similar customizability, designed as a successor to the Programmable Array Logic (PAL) chips which preceded them, and is likewise&nbsp;reprogrammable&nbsp;at will. The two are often used together.&nbsp;CPLDs&nbsp;have features, like the ability to operate with a minimum of&nbsp;peripheral&nbsp;devices, which make them a handy way to extend an&nbsp;FPGA design.The key for both&nbsp;FPGAs&nbsp;and&nbsp;CPLDs&nbsp;is that they&rsquo;re a blank slate. You are given the task of defining what the chip should do. If you change your mind you can modify the design at any time, or even replace it with something entirely different. This makes an&nbsp;FPGA&nbsp;extremely&nbsp;cost effective&nbsp;for&nbsp;prototyping&nbsp;and experimentation while helping to reduce&nbsp;time-to-market&nbsp;for small-scale production runs.<h1 dir="ltr">What is an ASIC?</h1>An ASIC is an&nbsp;application-specific integrated circuit&nbsp;(ASIC), meaning a packaged&nbsp;semiconductor&nbsp;with a fixed purpose matched to a formal&nbsp;specification. Exactly what the purpose is depends on its design. An ASIC may be used to decode a radio signal, or to control a motor, or even drive a smartphone or games console. Having only the resources it needs, and being tailored to a given task, means that it can operate at a&nbsp;high speed&nbsp;and more efficiently than a general-purpose processor or&nbsp;FPGA.<img src="https://images.wevolver.com/eyJidWNrZXQiOiJ3ZXZvbHZlci1wcm9qZWN0LWltYWdlcyIsImtleSI6ImZyb2FsYS8xNjU1MTI4MTE5Njk0LWltYWdlNC5qcGciLCJlZGl0cyI6eyJyZXNpemUiOnsid2lkdGgiOjk1MCwiZml0IjoiY292ZXIifX19" style="width: 300px;" class="fr-fic fr-dib" alt="A picture of an Allwinner D1 RISC-V system-on-chip, taken from the top down. It is attached to a Nezha development board.">The key differentiation in&nbsp;ASIC vs FPGA&nbsp;is that an ASIC is finalized at the foundry, where&nbsp;transistors&nbsp;and other components are placed, and cannot be changed once manufactured. If its purpose is retired or needs to be updated, the ASIC needs to be recycled and replaced with a newly-manufactured version. This stands in stark contrast with an&nbsp;FPGA, which can simply be provided with new gateware.There are numerous reasons why ASICs, and not&nbsp;FPGAs, are the prevalent component in modern&nbsp;high volume&nbsp;electronic devices, though. The question of&nbsp;ASIC vs FPGA&nbsp;is less clear-cut than it might at first seem.<h1 dir="ltr">Design Flow</h1>While early chip design involved drafting tables, set-squares, pens, and sticky tape &mdash; the latter living on in the terminology &ldquo;tape-out,&rdquo; when a design is laid out ready for manufacturing &mdash; the modern&nbsp;design flow&nbsp;for both ASICs and&nbsp;FPGAs&nbsp;is similar.In either case, a design is put together using a&nbsp;hardware description language&nbsp;(HDL) like&nbsp;Verilog&nbsp;or&nbsp;VHDL. The designer is effectively writing a program, but rather than software the result is instructions on how either a physical ASIC or the gateware of an&nbsp;FPGA&nbsp;should operate. Electronic design automation tools (EDA tools) are likewise available for both, providing a route to&nbsp;synthesis&nbsp;of an&nbsp;FPGA design&nbsp;or a tape-out for ASIC production.During the design process there&rsquo;s the requirement for testing. Here, ASICs and&nbsp;FPGAs&nbsp;begin to diverge: While both ASIC and&nbsp;FPGA&nbsp;HDL&nbsp;designs can be tested using simulation and formal verification, the&nbsp;FPGA design&nbsp;can be loaded onto an actual&nbsp;FPGA&nbsp;and tested in-circuit. The&nbsp;ASIC design, however, can only be committed to hardware as part of an expensive production run.Many&nbsp;ASIC designs&nbsp;&mdash; or, for more complex designs, sub-sections thereof &mdash; begin life as&nbsp;FPGA designs. Once tested in-circuit using an&nbsp;FPGA, the design is modified for production and sent to a fabrication facility for production as an ASIC. As a result, in many cases, it&rsquo;s less a question of &ldquo;ASIC&nbsp;vs&nbsp;FPGA&rdquo; and more &ldquo;ASIC&nbsp;and&nbsp;FPGA.&rdquo;<img src="https://images.wevolver.com/eyJidWNrZXQiOiJ3ZXZvbHZlci1wcm9qZWN0LWltYWdlcyIsImtleSI6ImZyb2FsYS8xNjU1MTI4MTMxMjE0LWltYWdlNS5qcGciLCJlZGl0cyI6eyJyZXNpemUiOnsid2lkdGgiOjk1MCwiZml0IjoiY292ZXIifX19" style="width: 300px;" class="fr-fic fr-dib" alt="A screenshot of Microchip's software tools for FPGA development, showing a template for a Verilog FPGA hardware definition."><h1 dir="ltr">Performance and Efficiency</h1>Despite their flexibility,&nbsp;FPGAs&nbsp;aren&rsquo;t magic. In order to offer high configurability, they require numerous resources internally. As a result, an&nbsp;HDL&nbsp;design loaded onto an&nbsp;FPGA&nbsp;will always require a larger and slower chip than the same design produced as an ASIC at an equivalent technology level. The ASIC can be specifically tailored to the task and hold only the resources required for that particular design, with no wastage.For the question of&nbsp;ASIC vs FPGA, this would seem to be a clear win for ASIC. Indeed, that&rsquo;s one of the key reasons why ASICs massively outnumber&nbsp;FPGAs&nbsp;in production devices, particularly at&nbsp;high volume&nbsp;scales.Recommended reading: <a href="https://www.wevolver.com/article/novel-hiddenite-accelerator-aims-to-offer-dramatic-improvements-in-deep-learning-energy-efficiency" target="_blank">Novel Hiddenite accelerator aims to offer dramatic improvements in deep-learning energy efficiency</a>.It&rsquo;s not a complete win for ASICs, though. If the choice is between an ASIC which has not been specifically tailored to a particular workload or an&nbsp;FPGA design&nbsp;which has gone through&nbsp;optimization, it&rsquo;s entirely possible for the&nbsp;FPGA&nbsp;to outperform the ASIC. This can be seen where&nbsp;FPGAs&nbsp;are increasingly being used as&nbsp;high-performance&nbsp;accelerators for specific workloads alongside general-purpose chips like&nbsp;CPUs&nbsp;and GPUs.Recommended reading: <a href="https://www.wevolver.com/article/designing-customized-brains-for-robots" target="_blank">Designing customized &quot;brains&quot; for robots</a>.<img src="https://images.wevolver.com/eyJidWNrZXQiOiJ3ZXZvbHZlci1wcm9qZWN0LWltYWdlcyIsImtleSI6ImZyb2FsYS8xNjU1MTI4MTQ3Mzk4LWltYWdlNi5qcGciLCJlZGl0cyI6eyJyZXNpemUiOnsid2lkdGgiOjk1MCwiZml0IjoiY292ZXIifX19" style="width: 300px;" class="fr-fic fr-dib" alt="A picture of a Microsemi SmartFusion 2 chip, attached to a PolarFire SoC Icicle Kit development board, taken from the top."><h1 dir="ltr">Power Consumption</h1>Larger chips mean more power, and it&rsquo;s here that the difference in&nbsp;ASIC vs FPGA&nbsp;really shows. Owing to their extremely generalized nature&nbsp;FPGAs&nbsp;are traditionally power-hungry devices. An ASIC, built on a modern technology platform, can draw such little power that it&rsquo;s even possible to drive a project using solely harvested energy.Recommended reading:&nbsp;<a href="https://www.wevolver.com/article/ultralow.power.chips.help.make.small.robots.more.capable" target="_blank">Ultra-low power&nbsp;chips help make small robots more capable</a>.Again, it&rsquo;s a question of exactly what you&rsquo;re comparing against. If you have a design where&nbsp;power consumption&nbsp;is key, the ASIC implementation will always be&nbsp;lower power&nbsp;than the&nbsp;FPGA&nbsp;implementation. If your choice is between running a workload on a general-purpose processor or an&nbsp;FPGA&nbsp;with gateware tailored to that specific task, it&rsquo;s entirely possible for the&nbsp;FPGA&nbsp;to run faster while simultaneously drawing&nbsp;less power.Recommended reading:&nbsp;<a href="https://www.wevolver.com/article/miniaturizing.the.brain.of.a.drone" target="_blank">Miniaturizing the brain of a drone</a>.FPGAs are steadily becoming more power-efficient, too. While they&rsquo;ll never come close to an equivalent ASIC, some modern FPGA devices like <a href="https://www.microchip.com/en-us/products/fpgas-and-plds/fpgas/polarfire-fpgas" target="_blank">Microchip&rsquo;s PolarFire and mixed-function PolarFire&nbsp;SoC&nbsp;(System on Chip) ranges</a> are designed for power efficiency. In many cases they can replace older-generation ASICs while requiring less power.<h1 dir="ltr">Configuration</h1>The configuration of an&nbsp;FPGA&nbsp;happens in the gateware, as generated from the&nbsp;HDL&nbsp;program written by the chip designer. It&rsquo;s flexible, and providing the&nbsp;FPGA&nbsp;has sufficient resources can be extended, shrunk, tweaked, or replaced. It does, however, rely on external components for bootstrapping, which is where a&nbsp;CPLD&nbsp;can assist.An ASIC&rsquo;s configuration is entirely fixed once manufactured. While minor changes can be made using software workarounds or microcode updates, there&rsquo;s no way to completely change the operation of the chip without physically replacing it.Recommended reading:&nbsp;<a href="https://www.wevolver.com/article/programmable-versus-fixed-function-controllers-alternatives-for-complex-robotic-motion" target="_blank">Programmable versus fixed-function controllers: Alternatives for complex robotic motion</a>.It&rsquo;s this inflexibility which has driven a reconsideration of the&nbsp;ASIC vs FPGA&nbsp;question, and increasing interest in combining the best of both worlds. Many larger&nbsp;ASIC designs&nbsp;now include embedded&nbsp;FPGA&nbsp;(eFPGA) capabilities.&nbsp;FPGAs&nbsp;have also become available which integrate ASIC components including general-purpose processors, so as to reduce the need for external hardware.<img src="https://images.wevolver.com/eyJidWNrZXQiOiJ3ZXZvbHZlci1wcm9qZWN0LWltYWdlcyIsImtleSI6ImZyb2FsYS8xNjU1MTI4MTYxNjc1LWltYWdlMy5qcGciLCJlZGl0cyI6eyJyZXNpemUiOnsid2lkdGgiOjk1MCwiZml0IjoiY292ZXIifX19" style="width: 300px;" class="fr-fic fr-dib" alt="A photograph of a computer processor, pin-side to camera, held in a stand so as to show as a diamond shape."><h1 dir="ltr">Barrier to Entry</h1>If this article had been written just a few years ago, the question of barrier to entry would have been a clear win for the&nbsp;FPGA. Producing physical ASICs is an undeniably complex undertaking and the software for it was often guarded behind high-priced licenses. Even then, once your&nbsp;HDL&nbsp;design had been tested in simulation, actually producing it would require considerable investment.Today, though, things are different. The rise of the free and open source silicon (FOSSi) movement has dramatically lowered the barrier to entry. Just as&nbsp;FPGA designers&nbsp;have long had the option of using fully-open toolchains, as promoted by organizations including the<a href="https://osfpga.org/" target="_blank">&nbsp;OSFPGA Foundation</a>, now&nbsp;ASIC designers&nbsp;can get started at zero cost. Educational programs like Matthew Venn&rsquo;s<a href="http://zerotoasiccourse.com/" target="_blank">&nbsp;Zero to ASIC course</a> offer an easily-approached introduction.Recommended reading: <a href="https://www.wevolver.com/article/enabling.anyone.to.design.hardware.with.a.new.opensource.tool" target="_blank">Enabling anyone to design hardware with a new open-source tool</a>.For now it&rsquo;s still easier to get started with&nbsp;FPGAs&nbsp;than&nbsp;ASIC designs, particularly for absolute beginners. A broader range of companies offer&nbsp;FPGA&nbsp;resources, from hardware to training, and toolchains are both well supported and heavily documented.<h1 dir="ltr">Analog&nbsp;blocks</h1>There&rsquo;s one key area where ASICs and&nbsp;FPGAs&nbsp;diverge dramatically:&nbsp;Analog&nbsp;support.&nbsp;FPGAs&nbsp;are primarily digital devices, concerned with digital logic, but not all electronics are digital.Recommended reading:&nbsp;<a href="https://www.wevolver.com/article/research-brings-analog-computers-just-one-step-from-digital" target="_blank">Research brings analog computers just one step from digital</a>.The majority of&nbsp;FPGAs&nbsp;available today are purely digital devices, offering any&nbsp;analog&nbsp;support as fixed-functional&nbsp;peripherals. While there is an equivalent for&nbsp;analog&nbsp;electronics, the field-programmable&nbsp;analog&nbsp;array (FPAA), they&rsquo;re not commonly seen.An ASIC, by contrast, can be manufactured using any physically-possible components including&nbsp;analog, digital, or a mixture of both. Where projects intrude on the&nbsp;analog&nbsp;domain, an ASIC will likely prove the only choice. Alternatively, a split design can be used with an&nbsp;FPGA&nbsp;taking care of the digital side and an ASIC or discrete off-the-shelf components handling&nbsp;analog&nbsp;work.<h1 dir="ltr">Cost</h1>The biggest decider when looking at&nbsp;ASIC vs FPGA&nbsp;is cost. For&nbsp;prototyping&nbsp;and even small-scale production, there&rsquo;s no question that&nbsp;FPGA&nbsp;wins out. Fully-functional&nbsp;FPGA&nbsp;hardware can be purchased for mere dollars, and the supporting software is usually provided free of charge for individuals and startups.ASIC companies, by contrast, have typically locked their &nbsp;process design kits (PDKs) behind expensive licenses or guaranteed minimum order quantities in the tens or hundreds of thousands. As a result, the non-recurring engineering cost (NRE cost) for ASIC design has been considerably higher than for FPGA work.Recommended reading: <a href="https://www.wevolver.com/article/addressing-the-microchip-shortage" target="_blank">Addressing the microchip shortage</a>.<img src="https://images.wevolver.com/eyJidWNrZXQiOiJ3ZXZvbHZlci1wcm9qZWN0LWltYWdlcyIsImtleSI6ImZyb2FsYS8xNjU1MTI4MTc2MzQ1LWltYWdlMi5qcGciLCJlZGl0cyI6eyJyZXNpemUiOnsid2lkdGgiOjk1MCwiZml0IjoiY292ZXIifX19" style="width: 300px;" class="fr-fic fr-dib" alt="A photo of components on a silicon wafer, before they are split up into individual dice. The image is taken at an angle, with a rainbow of colors reflecting from the silicon surface.">That&rsquo;s changing. Google&rsquo;s open-source division recently partnered with chip fab Skywater Technologies and&nbsp;ASIC design&nbsp;specialist Efabless to launch the<a href="http://developers.google.com/silicon" target="_blank">&nbsp;Open MPW Shuttle program</a>. The program lets anyone access a process design kit and a production slot to have physical ASICs built at zero cost, providing the design is released under an open-source license. For closed-source commercial designs, Efabless offers the alternative chipIgnite program which brings the cost to produce up to 300 ASICs to under $10,000. While far from cheap, it represents a&nbsp;unit cost&nbsp;a fraction of what it would have been just a few years ago.Recommended reading: <a href="https://www.wevolver.com/article/silicon-wafers-everything-you-need-to-know" target="_blank">Silicon wafers: Everything you need to know</a>.If you&rsquo;re scaling to production, though, there&rsquo;s no question as to the winner in the ASIC vs FPGA argument: When you&rsquo;re producing chips in the thousands, an ASIC implementation will always cost less per-chip than the equivalent design implemented in gateware on an FPGA. The more chips you produce the bigger that gap gets, which is the reason it&rsquo;s rare to see volume production of devices with FPGAs.<h1 dir="ltr">Conclusion</h1>There are plenty of reasons to choose to work towards implementing a chip design on an&nbsp;FPGA&nbsp;instead of an ASIC. For small-scale efforts that may well be the only choice &mdash; for now, at least. There are just as many reasons to aim for an ASIC implementation, however. This is particularly true where performance and power draw are more important than&nbsp;unit cost, or when a project scales into&nbsp;mass production.Taking the question of&nbsp;ASIC vs FPGA&nbsp;as a binary, however, is largely missing the point. The technologies are complementary, and as increasing volumes of ASICs ship with eFPGA components and&nbsp;FPGAs&nbsp;begin to increase their bundled ASIC blocks it&rsquo;s going to become increasingly difficult to draw a line between the two.Recommended reading: <a href="https://www.wevolver.com/article/a.new.hybrid.chip.that.can.change.its.own.wiring" target="_blank">A new hybrid chip that can change its own wiring</a>.Growing interest in free and open-source silicon is going to continue to push innovation for both FPGA and ASIC development, and will continue to drop the barriers to entry, too. If you&rsquo;ve never before considered delving into the world of ASICs and FPGAs, there has never been a better time.

There's never been a better time to dive into custom chip design, with both FPGA and ASIC design routes being more accessible than ever.