AI is moving beyond the data center and into the physical world. Vehicles, robots, industrial systems, sensors, and critical infrastructure increasingly rely on AI to perceive, decide, and act in real time. Physical AI refers to intelligent systems that sense, think, act, and communicate autonomously in platforms outside the data center, where software decisions have real-world consequences and must meet strict requirements for timing, safety, and reliability.Unlike cloud workloads that can tolerate latency and variability, Physical AI systems must respond predictably. A vehicle executing an emergency maneuver, a robotic arm adapting to changing conditions, or an industrial controller responding to a fault condition must process information and act within strict timing constraints. These workloads require predictable latency, low power consumption, functional safety, and close coordination between software and silicon.AI accelerators can identify objects, generate predictions, and process sensor data. Physical AI systems must also coordinate motion, manage safety functions, respond to changing conditions, and guarantee real-time behavior. Those requirements place equal importance on deterministic control and system orchestration. The MIPS many engineers remember as an embedded CPU company has evolved into the leading provider of RISC-V-based compute solutions, virtual platforms, and software-to-silicon development capabilities designed for Physical AI systems. This article explains what defines MIPS today and the engineering teams that benefit most from its technology.<h2>From Embedded CPU IP Vendor to an AI-Native Platform Company</h2>Since 2021, MIPS has embraced RISC-V as the architectural foundation for its next generation of compute solutions. RISC-V is an open instruction set architecture that allows companies to build differentiated processor implementations while benefiting from a shared ecosystem of software, tools, and operating system support.MIPS develops commercial processor IP, software tools, physical AI platforms, and custom application-specific standard products (ASSP) built on that foundation. MIPS uniquely combines compute architectures, virtual platforms, workload optimization, custom chip design, and manufacturing expertise into a unified software-to-silicon workflow.The company's software-to-silicon workflow consists of four stages:<ol><li>Understand and optimize workloads in a virtual platform.</li><li>Configure compute subsystems around workload requirements.</li><li>Optimize SoC architecture for performance, power, safety, and cost targets.</li><li>Manufacture and scale production using proven semiconductor processes.</li></ol>This workflow reflects a broader industry shift toward software-defined silicon development, where software requirements increasingly drive architectural decisions much earlier in the design process. An automotive developer can evaluate sensor-processing software in a virtual platform before silicon exists, identify bottlenecks, optimize the compute subsystem, and validate system behavior long before tape-out.<img src="https://s3-us-west-1.amazonaws.com/wevolver-project-images/froala%2F1786375561053-1786375561053.jpeg" width="624" height="428" class="fr-fic fr-dii" />RISC-V Processor. Source: AdobeStock.<h2>Why RISC-V is the Right Foundation</h2>RISC-V changes how companies access and customize processor architectures by separating the instruction set architecture from the processor IP built on top of it. This approach gives designers greater flexibility to optimize hardware around specific workloads while benefiting from a rapidly expanding ecosystem.There are four engineering arguments that matter: <ul><li>Modularity: RISC-V is designed as a small base instruction set with optional extensions. Designers start with the base and add only what the workload requires: AI extensions, security, DSP, or vector capabilities, instead of paying for and carrying instructions they will never execute.</li><li>Cost and Supply-Chain Independence: No upfront licensing fees, no per-chip royalties, and reduced exposure to single-vendor risk. For products shipping at high volume, the unit economics matters; whereas for products shipping into geopolitically sensitive markets, the supply-chain independence matters even more.</li><li>Architectural Flexibility: RISC-V allows workload-specific optimization and tighter hardware/software co-design than closed architectures permit. Teams can shape the ISA around the application, rather than the other way around.</li><li>Ecosystem Momentum: Multiple contributing companies, maturing toolchains, growing OS support, and an expanding developer base are turning what was a research architecture five years ago into a mainstream design choice today.</li></ul>The markets where these advantages are most valuable align closely with MIPS' strategic focus areas: automotive, aerospace and defense, robotics, industrial automation, intelligent infrastructure, IoT, and AI-enabled edge systems. These applications increasingly require workload-specific optimization, functional safety, and long product lifecycles that benefit from the flexibility of RISC-V.<h2>Why OEMs Are Seeking Greater Control Over Semiconductor Design</h2>The deeper force behind RISC-V adoption is that AI workloads are evolving faster than traditional silicon development cycles. By the time a fixed-architecture SoC ships, the workloads it was optimized for have often moved on. That mismatch has pushed OEMs to seek more control over workload-specific optimization, custom instruction extensions, hardware/software co-design, and long-term platform differentiation.Traditional fixed architectures can limit all four. They constrain how deeply teams can tune the silicon around proprietary workloads, and they tie product roadmaps to someone else's release schedule. RISC-V removes that ceiling. Companies can customize the architecture around their own workloads and reduce dependency on closed ecosystems they do not control.This broader industry shift toward software-first platform development, where the software stack, not the historical accumulation of architectural decisions, drives what the silicon needs to look like. Virtual platforms unlock these insights at the deepest levels by bringing software development into the architecture design stage of development. <img src="https://s3-us-west-1.amazonaws.com/wevolver-project-images/froala%2F1786375561058-1786375561058.jpeg" width="624" height="349" class="fr-fic fr-dii" />Futuristic robotic hand. Source: AdobeStock.<h2>Engineered for Physical AI and Real-Time Workloads</h2>MIPS focuses on <a href="https://mips.com/markets/physical-ai/" target="_blank" rel="noopener noreferrer">Physical AI</a>: intelligent systems that sense, understand, and act within the physical world. These systems include autonomous vehicles, industrial robots, aerospace platforms, intelligent machines, and edge infrastructure where software decisions have direct real-world consequences.This distinction separates Physical AI from cloud-centric AI. AI accelerators deliver throughput for perception and inference workloads, while deterministic compute coordinates system behavior, manages safety functions, and ensures that actions occur within predictable timing boundaries. Real-world systems require both capabilities.Many use cases follow from that:<ul><li>Automotive: sensor fusion, domain controllers, safety monitoring in zonal controllers, ADAS, and <a href="https://mips.com/wp-content/uploads/2025/11/Whitepaper-MIPS-P8700-for-ADAS-and-AD-SoCs-2-TM.pdf" target="_blank" rel="noopener noreferrer">autonomous driving</a>.</li><li>Aerospace and Defense: platforms that need functional safety, deterministic processing, and open stacks for AI inference </li><li>Industrial Automation and PLCs: for motion control, safety domains, and real-time event-driven applications</li><li>Autonomous Embedded Devices and Intelligent Sensors.</li><li>Robotics and Intelligent Edge Infrastructure.</li></ul>The engineering priorities across all of these are the same: low latency, predictable performance, and functional safety.<h2>The Atlas Explorer Virtual Platform </h2>The software-to-silicon flow requires tools that make the “software” component tangible and actionable, not aspirational. MIPS introduced Atlas Explorer, the software development and optimization platform for its Atlas portfolio of compute subsystems. Atlas Explorer enables engineering teams to: <ul><li>Implement shift-left optimization for software and platform, where tuning happens before silicon exists, not after.</li><li>Perform pre-silicon system-level testing of MIPS compute subsystems.</li><li>Create digital-twin modeling of the target platform, so software and silicon teams work from the same reference.</li><li>Gain data-driven insight into how workloads actually execute, not just how they were expected to.</li><li>Share reporting across software, hardware, and systems teams through a common view.</li></ul>By prioritizing a software-first methodology for silicon engineering, Atlas Explorer helps transform the concept of software-defined hardware into a practical development workflow. <img src="https://s3-us-west-1.amazonaws.com/wevolver-project-images/froala%2F1786375561064-1786375561064.jpeg" width="624" height="349" class="fr-fic fr-dii" />AI processors. Source: AdobeStock.<h2>Built for Modern, Heterogeneous SoCs</h2>Modern chips aren't built around a single general-purpose core anymore. They're built from workload-specific compute blocks: AI accelerators, DSPs, GPUs, and security engines stitched together on a single die.In increasingly heterogeneous systems, designers often deploy multiple classes of processors. MIPS and ARC provide complementary technologies optimized for different compute requirements, allowing architects to select the right engine for each workload. The role MIPS plays inside a heterogeneous SoC can vary from the control plane and real-time decision engine to embedded safety-capable applications processors and AI inference engines. It serves as the orchestration layer that coordinates the rest of the system and handles the safety-critical, time-sensitive decisions that throughput-oriented accelerators are not designed for.That role becomes more important, not less, as Physical AI systems mature. The more compute domains a system contains, such as vision acceleration, language models, sensor fusion, and motor control, the more it needs a deterministic core in the middle, making sure they all act together in real time.In increasingly heterogeneous SoCs, designers require multiple classes of compute optimized for different workloads. Together, MIPS and ARC provide complementary processor technologies that allow architects to deploy the right compute engine for each function, from real-time control and safety management to embedded intelligence and workload-specific processing.<h1><img src="https://s3-us-west-1.amazonaws.com/wevolver-project-images/froala%2F1786375561070-1786375561070.jpeg" width="624" height="208" class="fr-fic fr-dii" />MIPS</h1><h2>Who Needs MIPS?</h2>The three audiences MIPS is targeting today are OEMs, integrators, and IDMs. The needs are different for each market, but the underlying requirement is the same: deterministic, safety-aware compute that can be tuned to the workload. <h3>OEMs Building Safety-Critical Systems</h3>Automotive is one of the clearest examples of this trend. Software-defined vehicles, zonal architectures, ADAS platforms, automated driving systems, and vehicle control domains all require deterministic compute that meets stringent functional safety requirements. MIPS targets workloads where predictable latency, ASIL-oriented design, long lifecycle support, and real-time decision making are more important than raw application processor performance. The role of MIPS technology is to serve as the real-time compute layer that coordinates and controls safety-critical vehicle functions.<h3>Integrators Building Physical AI Systems</h3>Robotics companies, autonomous-system developers, industrial OEMs, and smart-infrastructure builders all share a common engineering need: deterministic response times, local decision-making without cloud dependence, and reliability over raw throughput. MIPS fits as the real-time compute layer alongside AI accelerators, and as the control core in PLCs, factory automation, and edge infrastructure where uptime and predictability matter more than peak FLOPS. <h3>IDMs Designing SoCs</h3>The third audience is the companies designing their own silicon: hyperscalers, system companies, and silicon startups building chips in-house, increasingly on RISC-V for the flexibility reasons described above. MIPS fits inside their designs as:<ul><li>The embedded "brain" for specialized chips (power ICs, RF, sensors, memory controllers) running firmware, managing power states, and handling communication protocols.</li><li>Area- and power-efficient cores for always-on subsystems.</li><li>A flexible licensing and royalty model that matters when products ship in high volume.</li><li>A platform suited to custom instruction extensions and tight hardware/software co-design.</li></ul>There is also an ecosystem continuity advantage. Some IDMs already have product lines built around MIPS, with existing software, toolchains, and team expertise. The path forward on RISC-V preserves that institutional investment rather than discarding it.<h2>The Bigger Picture and What Comes Next</h2><a href="https://mips.com/products/" target="_blank" rel="noopener noreferrer">MIPS today is a RISC-V-based compute company focused on enabling Physical AI systems through software-to-silicon development.</a> Its strategy combines compute IP, virtual platforms, software optimization, and manufacturing expertise to help customers build intelligent systems that operate safely, efficiently, and predictably in the physical world.This allows engineering teams to evaluate, optimize, and scale systems using a unified development approach. This alignment supports a growing industry shift toward software-defined silicon, where software and hardware are increasingly developed and optimized together rather than through traditional sequential handoffs.This article is the first in a series. Future pieces will examine RISC-V in next-generation SoCs, the Atlas Explorer platform, <a href="https://mips.com/blog/#whitepapers" target="_blank" rel="noopener noreferrer">MIPS</a> in automotive and Physical AI, how the new combined MIPS and ARC team will expand heterogeneous compute and embedded intelligence, and the patterns engineers should plan for as AI moves to the edge.

MIPS, by GlobalFoundries, is an early pioneer of the original reduced instruction set revolution and is now focused on enabling Physical AI systems with the modern, open RISC-V instruction set architecture.

How MIPS Is Powering Physical AI with RISC-V and Software-to-Silicon Development

Microprocessor vs Integrated Circuit (IC)

This article explains, how is a microprocessor different from an integrated circuit, exploring their key differences, architectures, technological advancements, and potential applications.

How is a Microprocessor Different from an Integrated Circuit?

The rise of Artificial Intelligence (AI) and Machine Learning (ML) has rapidly impacted today's global economy, influencing everything from healthcare to autonomous systems. As of 2023, 55% of organizations used AI in at least one business unit or function, compared to only 20% in 2017 [1].As it permeates more of our economies and daily lives, AI extends beyond the technical. Every country around the world needs to work out their strategy to unlock the potential of AI to solve local problems, while also being able to access the possibilities of a worldwide market. Now, as nations rush to harness the power of AI, it has become clear that the development of robust, performant, and efficient AI/ML computing resources is a global necessity.&nbsp;Enabling widespread access to AI/ML hardware and software is now a matter of global importance. RISC-V is a proven player in this effort. In this article, we’ll explore how RISC-V can transform the AI/ML sector, promote consensus-driven development and global collaboration, and bring socioeconomic benefits to countries around the world.<h1 dir="ltr">Improving Programmer Productivity With a Unified Model</h1>A unique aspect of RISC-V is its unified programming model, which enables the customized development of different types of processors, CPU, GPU and NPU, under a single, consistent set of instructions and interfaces. The model provides programmers with a standardized framework and common tools that enable them to easily write versatile and efficient code across different processing units.&nbsp;Through the use of a single architecture [2], RISC-V eliminates the need for separate programming paradigms for different processing units. As such, RISC-V reduces the learning curve and minimizes the overhead associated with switching between different architectures. Ultimately, this simplifies coding efficiency, reduces errors, and accelerates development cycles.The enhanced productivity facilitated by RISC-V can lead to a competitive edge in technological advancements. Global economies that embrace RISC-V can expedite their custom AI/ML developments to solve local problems and strengthen their positions in the global tech landscape through the adoption of the RISC-V standard. Ideally, this advantage translates into economic growth, job creation, and increased influence in the digital economy.Socioeconomically, RISC-V reduces barriers to entry for AI/ML development and democratizes access to advanced computing capabilities. Such democratization helps to encourage local innovation with worldwide impact across diverse sectors, driving societal progress, and improving quality of life.<h1 dir="ltr">Encouraging International Collaboration</h1>RISC-V is transforming the computing landscape by encouraging unprecedented levels of international collaboration [3].&nbsp;Specifically, the RISC-V industry standard Instruction Set Architecture (ISA) removes proprietary barriers, allowing developers, companies, and academic institutions worldwide to contribute to and benefit from the RISC-V architecture. In contrast to proprietary ISAs, where mainly major players have significant influence, RISC-V allows innovation to emerge from anywhere. It empowers smaller entities and individual contributors to take a first-hand approach in the technological revolution, resulting in a more equitable and dynamic technological ecosystem.The net effect of this openness is the fostering of a global community of innovators, all working cohesively to drive collaborative research and development across borders. By leveraging the collective intelligence and diverse perspectives of an international cohort, RISC-V presents an unprecedented opportunity to accelerate technological advancements in AI. Ultimately, the consensus-driven nature of RISC-V ensures that improvements and innovations are shared broadly.RISC-V is also unique in that, by adhering to a common set of standards, it enables unprecedented ease of integration and interoperability among hardware and software developed by different entities worldwide. As a result, companies, governments, universities and developers can work together more effectively, pooling their resources and expertise to tackle complex challenges collectively and push the state of the industry forward.&nbsp;The implications of this collaborative approach are significant. Nations that embrace RISC-V can enhance their technological capabilities through shared knowledge and resources. Brazil, for example, is developing AI infrastructure based on RISC-V, focused on High-Performance Computing (HPC), semiconductor technology, and large language models [4]. Such a collaborative spirit can lead to stronger international alliances and partnerships and drive economic growth and technological progress on a global scale.&nbsp;<h1 dir="ltr">Breaking Vendor Lock-In</h1>Finally, one of RISC-V’s most important value propositions is that it introduces a new paradigm in which developers and companies have a wider range of choices for AI processing. Namely, the RISC-V ISA enables the design and implementation of custom processors, and also for the RISC-V semiconductor ecosystem to develop a wider range of pre-developed AI chips to choose from. Expertise and technologies from the RISC-V ecosystem of members can support any development, with a breadth of choice that also prevents your choice of AI vendor creating a long term dependency. &nbsp;By eliminating vendor lock-in, RISC-V enables developers to work faster, be more creative, and explore more flexible and rapid development cycles. RISC-V can further support the development and use of advanced technologies without restrictions on innovation. Where the goal is to create an equitable AI/ML landscape, RISC-V can help regions innovate independently, foster local talent, and establish a robust technological infrastructure that supports long-term growth and sustainability, while also maintaining access to a global market and ecosystem of partners.The benefits of breaking vendor lock-in extend significantly to the automotive industry, for example, which is currently undergoing its own set of transformations. Here, RISC-V offers the flexibility needed to innovate and remain competitive on a global scale. As cars become more and more defined by software workloads, including increased use of AI, manufacturers can leverage RISC-V to develop bespoke hardware solutions tailored to the specific needs of their markets [5], ensuring they keep pace with or even surpass their global competitors.&nbsp;Overall, by freeing the industry from vendor lock-in, RISC-V can give developers worldwide, and &nbsp;regions like Europe and Brazil, the tools needed to lead technological innovation and develop true digital sovereignty.&nbsp;<h1 dir="ltr">Conclusion&nbsp;</h1>The modern emergence of AI/ML is more than a simple technical phenomenon; it’s a movement with significant worldwide implications. As nations strive for digital sovereignty, RISC-V offers the tools needed to build robust, independent technological infrastructures while also enabling access to a global market and ecosystem of partner expertise.RISC-V is truly a catalyst for an equitable and collaborative future in AI and ML. As the importance of global deployment of AI/ML continues to grow, RISC-V will undoubtedly have a major role to play in the future of computing around the world.&nbsp;<h1 dir="ltr">References</h1>[1] <a href="https://aiindex.stanford.edu/report/" target="_blank">https://aiindex.stanford.edu/report/</a>[2]&nbsp;<a href="https://riscv.org/technical/specifications/" target="_blank">https://riscv.org/technical/specifications/</a>&nbsp;[3]<a href="https://riscv.org/blog/2023/10/risc-v-an-open-standard-backed-by-a-global-community-to-enable-open-computing-for-all/" target="_blank">https://riscv.org/blog/2023/10/risc-v-an-open-standard-backed-by-a-global-community-to-enable-open-computing-for-all/</a>[4]<a href="https://riscv.org/blog/2024/09/advancing-ai-the-brazilian-way-fostering-innovation-through-collaboration-and-open-standards/" target="_blank">https://riscv.org/blog/2024/09/advancing-ai-the-brazilian-way-fostering-innovation-through-collaboration-and-open-standards/</a>&nbsp;[5]<a href="https://riscv.org/blog/2024/08/infineon-harness-the-power-of-risc-v-for-next-generation-automotive-mcu-innovation/" target="_blank">https://riscv.org/blog/2024/08/infineon-harness-the-power-of-risc-v-for-next-generation-automotive-mcu-innovation/</a>

RISC-V offers the tools needed to foster local AI innovation while also enabling worldwide collaboration and access to a global market 

How RISC-V Changes the Global Landscape of AI and ML

The emergence of Artificial Intelligence (AI) and Machine Learning (ML) is one of the most significant computing trends in recent history. According to research, by 2027, spending on AI software alone will grow to nearly $300B, with a CAGR of 19.1% [1]. And, as the software half of the AI/ML world is growing at meteoric rates, the hardware side is also teeming with innovation. Similar research suggests that the AI accelerator market will increase from $21B in 2024 to $33B by 2028 [2].AI/ML is a software-driven pursuit and can have very different requirements depending on the market and application (i.e., automotive, IoT, cloud, training vs inference, etc). Supporting this fast moving and diverse software market requires a collaborative,industry-wide effort to develop flexible and customized domain-specific hardware solutions optimized for this range of AI workloads. Innovation means that the market should not be limited to a few key players. Rather, the process needs to be democratized to enable everyone, enterprises and startups, to contribute their ideas to the growing AI/ML computing landscape.&nbsp;RISC-V has become a preferred standard for designing the industry’s most performant and efficient AI/ML computing resources. Let’s take a look at what’s happening in the world of RISC-V for AI/ML and discover why RISC-V is a key technology for supporting the industry’s future.&nbsp;<h1 dir="ltr">Why RISC-V for AI/ML?</h1>RISC-V is a compelling architecture for the development of AI/ML systems.The extensible industry standard RISC-V ISA enables a software-focused approach to AI hardware, freeing developers from the restrictions of proprietary compute. RISC-V provides a common language for AI development, as an industry standard ISA, creating a cohesive ecosystem for AI/ML development. This robust and highly capable ecosystem of member companies, organizations, technologists, enthusiasts and academics, brings the expertise and technologies that can deliver future generations of innovative new AI systems.<h2 dir="ltr">Software-Focused Hardware</h2>RISC-V introduces new paradigms to the world of hardware design by enabling the concept of software-focused hardware. AI/ML is software defined, built on frameworks such as TensorFlow, ONNX and OneAPI, and rapidly evolving algorithms. Transformers, the basis of the recent boom in AI were <a href="https://research.google/pubs/attention-is-all-you-need/" target="_blank">only introduced in 2017</a>. New algorithms will emerge, requiring new hardware to run on, and while it is not possible to predict these algorithms, by using RISC-V we can prepare to support them with optimized hardware delivered fast.&nbsp;Historically, software designers have been constrained by the restrictions of proprietary hardware platforms. The development process involved designing applications to the constraints of predefined hardware, ultimately limiting performance and efficiency. Not every AI/ML workload belongs on a GPU. Instead of developing software to fit the constraints of predefined hardware, RISC-V’s modular architecture enables industry leading differentiation, through the development of custom processors and accelerators developed precisely for the requirements of specific AI workloads such as energy efficient IoT and powerful HPC applications.&nbsp;The configurability and openness of RISC-V enables a “software-focused” design paradigm, wherein hardware customization for specific workloads becomes feasible without the constraints imposed by proprietary instruction sets. This is achieved through RISC-V’s modular architecture, which allows developers to define custom extensions and instructions tailored to their unique workloads. For example, in AI/ML applications, developers can implement specialized instructions for matrix multiplications and vector processing—key operations in neural network computations.Using custom instructions, such as Single Instruction, Multiple Data (SIMD) operations, RISC-V processors can execute multiple data points with a single instruction, significantly boosting performance in parallel processing tasks common in AI/ML workloads. Additionally, hardware accelerators tailored to AI tasks can be integrated seamlessly. These accelerators, including tensor processing units (TPUs) or specialized neural processing units (NPUs), are designed to handle the intensive mathematical operations required for deep learning models, such as convolutions and backpropagation.This high degree of customization leads to superior computational efficiency, as the processor is optimized for specific tasks rather than relying on a generic, one-size-fits-all solution. Moreover, RISC-V’s ability to support fine-grained power management techniques reduces power consumption. For instance, designers can implement dynamic voltage and frequency scaling (DVFS) tailored to the specific needs of AI/ML tasks, reducing power usage without compromising performance.Furthermore, the RISC-V standard promotes rapid innovation and cost-effective development. Developers can contribute to and benefit from a global ecosystem of shared knowledge and resources, facilitating rapid innovation and ultimately a faster time-to-market. This collective effort ensures that the latest advancements in AI/ML can be quickly integrated into hardware designs, keeping pace with the fast-evolving demands of the field.<h2 dir="ltr">Creating a Common Language</h2>The RISC-V instruction set architecture (ISA) provides a uniform language for hardware and software developers, creating a cohesive ecosystem for AI/ML development. It allows developers to create tailored domain specific solutions with greater flexibility. Importantly, the controlled way in which this is enabled ensures that the base foundational software elements, such as those running on Linux, remain consistent and interoperable across different RISC-V implementations.Ultimately, RISC-V's unique proposition lies in its ability to foster AI/ML by leading the industry in providing the opportunity to build customized and differentiated solutions from standard and non-standard extensions. This enables domain-specific acceleration while maintaining the productivity benefits of a single, coherent programming model. RISC-V defines a small base feature set for implementers to use along with ratified extensions which they can use as required. Inside a single RISC-V based AI/ML SoC you can deeply customize different RISC-V cores for different jobs such as SoC Control or matrix multiplication, with these different cores all based on the same ISA, making them easier to program.&nbsp;To add to this flexibility, RISC-V permits the addition of vendor-specific extensions to differentiate products with application-specific functionality. RISC-V provides guidance and branding to implementors for interoperability requirements in market segments through the definition of “RISC-V Profiles"Offering a standardized yet flexible platform allows designers to rapidly integrate cutting-edge research into hardware without being hampered by proprietary constraints. Developers can leverage community contributions, such as optimized libraries and toolchains, to expedite the development process and enhance the performance of their AI/ML solutions.Beyond this, the RISC-V ISA presents a significant advantage in providing standardized, modular building blocks for various computing applications. This standardization enables hardware designers to develop and integrate components more seamlessly, reducing the complexity and cost typically associated with custom designs.By making custom designs more accessible, RISC-V makes an easier business case for the creation of optimized platforms for specific use cases, rather than compromise on having to use more generic hardware and software created for other high volume markets.&nbsp;<h2 dir="ltr" id="isPasted">A Highly Capable Ecosystem Delivering AI/ML Solutions on RISC-V </h2>The capabilities of the RISC-V member ecosystem enables AI developers to deliver the innovative software focused AI systems. From processor IP to design services and simulation to software components, the collective knowledge of these companies and organizations covers all the capabilities required to create custom software-focused AI/ML processing, enabling developers to concentrate on their innovation. The range of choice from this healthy market of ecosystem members prevents vendor lock-in and mitigates some of the supply chain challenges faced by other architectures. Alongside the capability to create custom processing, the RISC-V ecosystem also offers a range of pre-designed AI silicon, designed for different workloads.There’s no doubt that this RISC-V ecosystem has taken a foothold in the industry at large. In fact, so far, we estimate that more than 10 billion RISC-V processor cores have shipped [3]. Now, we’re seeing similar adoption in the AI/ML hardware markets, where reports are indicating that RISC-V-based AI SoCs will have a CAGR for units of 73.6% by 2027, while AI SoC unit shipments are projected to reach 25B by then. [4]. RISC-V is quickly becoming the defacto standard for building AI accelerators.&nbsp;Here are some of the highlights of RISC-V’s use in AI/ML.<ul><li dir="ltr">Meta’s MTIA v1 AI Inference Accelerator [5]</li><li dir="ltr">Esperanto ET-SoC-1 [6]</li><li dir="ltr">Google’s TPU [7]</li><li dir="ltr">SiFive Intelligence X390 [8]</li><li dir="ltr">StreamComputing STPC920 [10]</li><li dir="ltr">Ventana Veyron V2 [11]</li><li dir="ltr">Andes Technology QiLai SoC [12]</li><li dir="ltr">Semidynamics ‘All-In-One AI’ IP [13]</li><li dir="ltr">Axelera AI Metis AI Platform [14]</li><li dir="ltr">Project Open Se Cura [15]</li><li dir="ltr">Codeplay oneAPI Construction Kit [16]</li></ul><h1 dir="ltr">Conclusion</h1>As the AI/ML market continues to grow exponentially, RISC-V is poised to be a formidable driver of innovation and change for all. By offering a modular, open, and customizable architecture, RISC-V gives designers the creativity, power, and speed of innovation needed to address the diverse and evolving needs of AI/ML applications. Developers are empowered with the flexibility to tailor solutions to specific requirements while working in a unified and interoperable ecosystem. Finally, the community-driven innovation model of RISC-V accelerates the development of cutting-edge technologies and democratizes access to advanced hardware design for all.For more information on how RISC-V is driving the future of AI, visit <a href="http://www.riscv.org/ai" target="_blank">www.riscv.org/ai.</a><h1 dir="ltr">References</h1>[1]<a href="https://www.gartner.com/en/documents/4925331#:~:text=Summary,2023%20to%2035%25%20by%202027" target="_blank">https://www.gartner.com/en/documents/4925331#:~:text=Summary,2023%20to%2035%25%20by%202027</a>.[2] <a href="https://www.gartner.com/en/newsroom/press-releases/2024-05-29-gartner-forecasts-worldwide-artificial-intelligence-chips-revenue-to-grow-33-percent-in-2024#:~:text=Gartner%20forecasts%20AI%20PC%20shipments,will%20be%20an%20AI%20PC" target="_blank" rel="noopener noreferrer">https://www.gartner.com/en/newsroom/press-releases/2024-05-29-gartner-forecasts-worldwide-artificial-intelligence-chips-revenue-to-grow-33-percent-in-2024#:~:text=Gartner%20forecasts%20AI%20PC%20shipments,will%20be%20an%20AI%20PC</a>.[3]<a href="https://riscv.org/news/2022/07/europe-steps-up-as-risc-v-ships-10bn-cores-nick-flaherty-ee-news-europe/" target="_blank">https://riscv.org/news/2022/07/europe-steps-up-as-risc-v-ships-10bn-cores-nick-flaherty-ee-news-europe/</a>[4] <a href="https://semico.com/content/analyzing-risc-v-cpu-market-sip-socs-ai-and-design-starts" target="_blank" rel="noopener noreferrer">https://semico.com/content/analyzing-risc-v-cpu-market-sip-socs-ai-and-design-starts</a>[5]<a href="https://ai.meta.com/blog/meta-training-inference-accelerator-AI-MTIA/" target="_blank">https://ai.meta.com/blog/meta-training-inference-accelerator-AI-MTIA/</a>[6]<a href="https://www.esperanto.ai/products/" target="_blank">https://www.esperanto.ai/products/</a>[7] <a href="https://riscv.org/wp-content/uploads/2018/12/Antmicro-RISC-V-Summit-Keynote.pdf" target="_blank" data-lf-fd-inspected-kn9eq4roawkarlvp="true">https://riscv.org/wp-content/uploads/2018/12/Antmicro-RISC-V-Summit-Keynote.pdf</a>[8] <a href="https://www.sifive.com/cores/intelligence-x390" target="_blank">https://www.sifive.com/cores/intelligence-x390</a>[9] <a href="https://tenstorrent.com/hardware/wormhole" target="_blank">https://tenstorrent.com/hardware/wormhole</a>&nbsp;[10] <a href="https://www.streamcomputing.com/en/index.php?s=product&c=category&id=2" target="_blank">https://www.streamcomputing.com/en/index.php?s=product&amp;c=category&amp;id=2</a>[11] <a href="https://www.ventanamicro.com/ventana-introduces-veyron-v2/" target="_blank">https://www.ventanamicro.com/ventana-introduces-veyron-v2/</a>[12] <a href="https://www.andestech.com/en/2024/05/30/andes-technology-announced-the-qilai-soc-and/" target="_blank">https://www.andestech.com/en/2024/05/30/andes-technology-announced-the-qilai-soc-and/</a>[13] <a href="https://semidynamics.com/en/resources/press-releases" target="_blank">https://semidynamics.com/en/resources/press-releases</a>[14] <a href="https://www.axelera.ai/blog/the-metis-ai-platform-in-detail" target="_blank">https://www.axelera.ai/blog/the-metis-ai-platform-in-detail</a>[15] <a href="https://opensource.googleblog.com/2023/11/project-open-se-cura-open-source-announcement.html" target="_blank">https://opensource.googleblog.com/2023/11/project-open-se-cura-open-source-announcement.html</a>[16] <a href="https://developer.codeplay.com/products/oneapi/construction-kit/home/" target="_blank" rel="noopener noreferrer">https://developer.codeplay.com/products/oneapi/construction-kit/home/</a>

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