New 64-bit RISC-V soft SoC for FPGAs with 8 GB DRAM reach
Up to four 64-bit RISC-V cores, a coherent L2 cache and a Linux-capable Sv39 MMU built from FPGA logic.
01 Oct, 2026. 5 minutes read
September 28th 2026 Efinix announced the Sapphire RV64 soft SoC
The Sapphire RV64's CPU cores, caches and peripherals are built from FPGA logic, with DRAM reached through the FPGA's hardened DDR interface. It uses one to four cores derived from VexiiRiscv, an MIT-licensed open-source RISC-V CPU. Each core has a seven-stage in-order pipeline implementing RV64IM with optional A, F, D, C, Zba, Zbb, Zbs and Zicbom extensions; Efinix lists Linux support via an optional Sv39 MMU.[1][2][3]
Efinix aims it at designs that have "outgrown the performance, addressable memory, cache, and I/O limits of 32-bit embedded cores". Support covers all Efinix's Titanium and Topaz FPGAs (its 16 nm families) and Trion devices (its first-generation 40 nm family) from the T20 up.[1][4][5]
Why it matters
The step from the company's 32-bit Sapphire SoC is mostly about memory. The 32-bit version addresses up to 3.5 GB of DRAM and has L1 caches only. Sapphire RV64 addresses up to 8 GB of DDR3 or LPDDR4x and adds a shared 64 to 512 KB L2 cache.[2][6] With the L2 enabled, it also keeps two AXI DMA ports from user logic coherent, so accelerators in the fabric share cached memory without software flushes.[2]
The 32-bit Sapphire already runs Linux; Efinix's br2-efinix Buildroot tree now builds Linux 6.6 for Sapphire RV64 too, so far only for the Titanium Ti375 C529 development board.[7][8] The gain is address reach: Sv39 gives software a 512 GB virtual address space, and the physical map places 8 GB of DRAM and a 64 GB cached AXI window above the 4 GB a 32-bit address spans.[2]
Raw speed is modest. On the Ti375 board one Sapphire RV64 core scores 1.23 to 1.57 CoreMark/MHz, and fMAX is 250 to 278 MHz on the Ti375 and 65 to 77 MHz on a Trion T120. On that T120, the nearest published 32-bit Sapphire configuration reaches 115 MHz in 7,391 logic/adders, against 77 MHz and 10,741 for the most basic 64-bit build.[2][9] The Ti375 also carries a hardened quad-core 32-bit RISC-V block, which Efinix benchmarks at 2.345 CoreMark/MHz at 1 GHz.[10][11][12] Multiplying score by clock (our calculation, if per-MHz scores hold across clocks and compilers), the best soft configuration gives about 400 CoreMark per core, a hard core about 2,300.
Where a hard CPU exists, Sapphire RV64's case rests on memory reach: up to 8 GB of DRAM against the hard block's 3.7 GB, and two cache-coherent DMA ports against its one AXI slave. It fits best on Trion, on Titanium and Topaz parts without the hardened block, and in 32-bit Sapphire designs that need more memory.[2][12][13]
AMD's MicroBlaze V soft core already offers a 64-bit Sv39 implementation, with a Linux preset listed at 199 to 258 MHz on UltraScale+ devices; Lattice's RISC-V RX is 32-bit.[14][15][16]
Technical specifications
Sapphire RV64 SoC: configurable range
Spec | Value |
|---|---|
CPU | 1 to 4 VexiiRiscv cores, 7-stage in-order pipeline, little-endian; machine and supervisor modes |
ISA | RV64IM; optional A, F, D, C, Zba, Zbb, Zbs, Zicbom |
System clock setting | 20 to 400 MHz (achieved clock limited by device fMAX) |
L1 cache | Instruction and data, 1, 2, 4 or 8 ways of 4 KB each; write-back data cache |
L2 cache | Optional, shared, 64, 128, 256 or 512 KB, 8-way; coherency point for DMA |
On-chip RAM | 4 to 512 KB, with SPI flash boot loader |
External memory | DDR3 at 800 Mbps, LPDDR4x at 3,200 Mbps, HyperRAM at 500 Mbps; 4 MB to 8 GB; DDR requires the FPGA's hardened DDR controller (Trion's supports DDR3, LPDDR3 and LPDDR2) |
Memory bus | AXI4 full-duplex or AXI3 half-duplex, 32 to 512 bits |
User-logic ports | Up to 2 coherent AXI4 slave (DMA) ports, 32 to 512 bits; up to 2 AXI4 master ports: A (AXI-Lite compatible, 256 MB uncached I/O region) and B (burst-capable, 64 GB cached region) |
Memory management | Optional Sv39 MMU; optional PMP at 4 KB granularity |
Interrupt handling | PLIC and CLINT; direct-mode trap vectors only (no vectored mode) |
Other options | FPU (single or single plus double precision); BTB, RAS and gshare branch predictor; hardware and software prefetchers; custom-instruction interface with 1,024 IDs |
Peripherals | Up to 32 GPIO, 5 I2C, 3 SPI, 3 UART, 3 timers, 8 user interrupts, 5 APB3 slave ports; watchdog |
Debug | RISC-V debug specification through the FPGA's JTAG User TAP, up to 4 hardware breakpoints, co-debug with the FPGA debugger; no GPIO-based soft debug TAP |
Linux support | br2-efinix Buildroot tree: Linux 6.6, U-Boot 2025.01, OpenSBI 1.6; RV64 build for the Titanium Ti375 C529 development board |
Supported FPGAs | All Titanium and Topaz; Trion T20 and above |
License terms and price | Not stated |
Sapphire RV64 single-core benchmark configurations (Efinix's Efinity design software, version 2026.1)
Spec | Basic L1 | Basic L2 | Advanced L1 | Advanced L2 |
|---|---|---|---|---|
CoreMark/MHz (Ti375 board) | 1.23 | 1.25 | 1.56 | 1.57 |
Dhrystone/MHz (Ti375 board) | 1.17 | 1.17 | 1.37 | 1.54 |
fMAX, Titanium Ti375 C529 | 271 MHz | 278 MHz | 250 MHz | 252 MHz |
fMAX, Topaz Tz170 J484 | 176 MHz | 170 MHz | 164 MHz | 167 MHz |
fMAX, Trion T120 F324 | 77 MHz | 77 MHz | 65 MHz | 65 MHz |
Logic/adders, Ti375 | 10,740 | 14,258 | 23,838 | 27,250 |
Memory blocks, Ti375 | 91 | 188 | 128 | 225 |
DSP48 blocks, all three devices | 17 | 17 | 17 | 17 |
Sources: [1][2][5][8][17]
All four configurations use 1-way 4 KB L1 caches and a 256-bit AXI4 memory bus; the L2 variants add 64 KB of L2. Basic enables the I, M, A and C extensions; Advanced enables every extension except Zicbom plus all optional features.[2] All published figures are single-core. Advanced roughly doubles logic for about a quarter more CoreMark/MHz, and at each configuration's Ti375 fMAX the gain narrows to about 14% (our calculation: 27,250 against 14,258 logic/adders; 252 × 1.57 against 278 × 1.25). Efinix notes that enabling custom instructions, the FPU or the Linux MMU affects fMAX.[17]
Recommended Reading: RISC-V Architecture: A Comprehensive Guide to the Open-Source ISA. Background on the RV32 and RV64 base ISAs, the standard extensions and the privilege modes that an Sv39 MMU relies on.
References
Efinix Brings 64-Bit RISC-V Performance to Embedded FPGA Designs With New Sapphire RV64 SoC, Efinix, 28 September 2026. Company press release.
Sapphire RV64 SoC Data Sheet, DS-SAPPHIRE-RV64 v1.0, Efinix, May 2026.
VexiiRiscv, SpinalHDL, accessed 30 September 2026. Open-source project repository.
Efinix Releases Topaz Line of FPGAs, Delivering High Performance and Low Power to Mass Market Applications, Business Wire, 11 July 2024. Company press release.
Trion FPGA Overview v3.3, Efinix, 2025.
Sapphire RV32 SoC Data Sheet: Features, Efinix, accessed 1 October 2026.
Linux + RISC-V Sapphire SoC, Efinix, accessed 1 October 2026.
BR2-Efinix: Buildroot external tree for building Linux for Efinix RISC-V Sapphire SoC, Efinix, branch 2025.02, accessed 1 October 2026. Company board support package.
Sapphire RISC-V SoC, Efinix, accessed 1 October 2026. Product page for the 32-bit soft SoC, with resource and fMAX tables.
Efinix's Titanium Ti375 Sampling; Unlocking and Delivering Mainstream Edge Intelligence Innovation, Business Wire, 1 April 2024. Company press release.
High-Performance Sapphire SoC User Guide: Performance, Efinix, accessed 30 September 2026. Vendor benchmark results.
High-Performance Sapphire RV32 SoC Data Sheet: Features, Efinix, accessed 1 October 2026.
High-Performance Sapphire RV32 SoC, Efinix, accessed 1 October 2026. Product page for the hardened block.
MicroBlaze V Processor Reference Guide (UG1629): Resource Utilization, AMD, release 2026.1, 31 July 2026.
MicroBlaze V Processor Reference Guide (UG1629): Memory Architecture, AMD, release 2026.1, 31 July 2026.
RISC-V RX CPU IP Core, Lattice Semiconductor, accessed 30 September 2026.
Sapphire RV64 SoC User Guide, UG-SAPPHIRE-RV64 v1.0, Efinix, May 2026.