What is VHDL? A Complete Guide with Syntax, Examples & IEEE Standards

TL;DR

VHDL is a hardware description language used to model digital systems from gate-level primitives up to system-level architectures. Unlike software programming languages, an HDL describes concurrent hardware behavior rather than sequential instruction flow. VHDL models can be simulated to verify functionality and then synthesized into gate-level netlists for implementation on FPGAs or ASICs.

Key Takeaways

• VHDL remains widely used in FPGA and ASIC development. Developed under the U.S. VHSIC program in the 1980s, the language became an IEEE standard (1076) and is still used for field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) development, especially in safety-critical industries [1].

• Strong typing aids reliability. VHDL's Ada-derived type system helps enforce predictable and deterministic hardware descriptions and catches many errors at compile time, whereas Verilog is weakly typed [1]. Military and aerospace organizations still prefer VHDL for mission-critical designs [1].

• Standard libraries matter. The IEEE 1164 std_logic_1164 package defines a nine-valued logic system (std_logic and std_ulogic), while numeric_std introduces UNSIGNED and SIGNED types with overloaded arithmetic functions [2][3]. Using these libraries avoids vendor-specific extensions.

• Different modelling styles. VHDL supports dataflow (concurrent signal assignments), behavioral (processes with sequential statements), and structural (component instantiation) descriptions. Each style serves different abstraction levels [5].

• Modern toolchains support VHDL-2008 and beyond. AMD Vivado 2024.x and Intel Quartus Prime support many VHDL-2008 features such as matching operators, process(all), and improved generate constructs [7][8]. Modern FPGA and simulation toolchains, including AMD Vivado and GHDL, increasingly support VHDL-2019 features such as interfaces and 64-bit integers, enabling designers to take advantage of newer language capabilities  [7][11].

• Verification frameworks thrive. Testbenches rely on non-synthesizable constructs and assertions; modern frameworks like OSVVM and VUnit provide random stimulus, functional coverage, and reusable verification components [14][15].

Introduction

VHDL grew out of the VHSIC (Very High Speed Integrated Circuit) program initiated by the U.S. Department of Defense. The program required a robust hardware description language (HDL) for specifying and simulating complex digital circuits. In 1987, the IEEE ratified the first VHDL standard (IEEE 1076) and later issued revisions in 1993, 2000, 2002, 2008, and 2019.

More than three decades later, VHDL remains a cornerstone of FPGA and ASIC workflows. Its strongly typed, Ada-inspired syntax enforces deterministic semantics and early error detection, qualities prized in aerospace, defense, medical, and automotive applications [1]. 

This article serves as a comprehensive reference for engineers and students who want to learn or refresh VHDL. It covers fundamental language constructs, data types, modelling styles, testbench methodologies, vendor tool support (AMD Vivado 2024.x, Intel Quartus Prime, Lattice Radiant, Microchip Libero, GHDL, and Yosys), comparisons with Verilog and SystemVerilog, common pitfalls, and modern extensions such as VHDL-2008 and VHDL-2019.

What Is VHDL?

VHDL History & IEEE Standardization

The language's design emphasises strong typing and predictable behaviour.. A U.S. Federal Aviation Administration report on safety-critical hardware notes that VHDL is "a strongly typed language derived from Ada and is widely used in military applications," whereas Verilog is modeled on C and widely used in the semiconductor industry [1]. Because VHDL enforces type checking, many errors are caught at compile time instead of during simulation. For high-assurance systems (DO-254 or similar), predictable and analyzable behavior can simplify verification and certification activities.

VHDL Standard Version History

VHDL vs Verilog vs SystemVerilog

Type System and Determinism

VHDL and Verilog sit at opposite ends of the type-system spectrum. VHDL is strongly and richly typed, derived from the Ada programming language; it requires explicit type declarations and conversions, catching signal-width mismatches at compile time rather than in simulation or silicon. Verilog, rooted in C and an earlier HDL called Hilo, uses predefined types only and permits implicit bit-level casting across them. This makes Verilog concise and fast to write, but allows ambiguous constructs — particularly hazardous when non-blocking assignments interact with multiple drivers. VHDL's determinism is language-enforced; Verilog's is conditional on the designer following strict coding conventions, and there is no compiler mechanism to guarantee compliance. SystemVerilog sits between the two: its newer constructs introduce stronger typing, but the Verilog-compatible core retains the original weak-typing behaviour.

Recommended Reading: Verilog vs VHDL: A Comprehensive Comparison

Verification Capability

Both VHDL and Verilog provide basic testbench support through signal driving and procedural blocks, but neither was designed with large-scale verification methodologies in mind. SystemVerilog was. Standardised as IEEE 1800 (most recently revised as IEEE 1800-2023), it is formally defined as a unified hardware design and verification language — not merely a verification add-on. Its object-oriented class system, interface constructs, SystemVerilog Assertions (SVA), and constrained-random stimulus generation make it the backbone of UVM-based verification environments that are now standard in ASIC development.

Domain Fit and Market Position

Language choice in practice is often driven by domain rather than raw capability. Verilog's conciseness makes it attractive for rapid ASIC prototyping in commercial semiconductor teams, while SystemVerilog has become the dominant verification language across that same industry. VHDL, however, holds a stronger position in FPGA design than its reputation suggests — the 2022 Wilson Research Group Functional Verification Study found it still leads in worldwide FPGA RTL adoption — and it remains the mandated or strongly preferred choice in defence, avionics, and safety-critical industrial programmes, where its determinism and comprehensive type system directly support certification requirements.

VHDL Design Units

A VHDL compilation unit consists of design units: entities, architectures, configurations, packages, and package bodies. These units define interfaces, implementations, and reusable definitions.

Entity Declarations

An entity defines the interface of a hardware block. It lists port names, directions, and data types, but contains no implementation. For example, a half-adder entity declares two one-bit inputs and two outputs:

entity half_adder is
  port (
    a, b : in  std_logic;  -- inputs
    sum  : out std_logic;  -- sum output
    carry: out std_logic   -- carry output
  );
end entity half_adder;

The VHDL-Online tutorial emphasizes that the entity describes only the interface and that ports with the same mode and type may be grouped [4]. Ports default to mode in, but explicit modes (in, out, inout, buffer) clarify how signals are driven. Entities are often stored in the work library; vendor tools compile each design unit into a library.

Further reading: The Ultimate Guide to ASIC Design: From Concept to Production

Architectures

An architecture provides the implementation for a specific entity. An entity may have multiple architectures (e.g., behavioral vs structural). Each architecture contains a declarative region - in which signals, types, constants, components, subprograms, and aliases may be declared and a concurrent statement region that describes behavior. The same half-adder can be implemented using concurrent signal assignments:

VHDL recognises three modelling styles within an architecture body: dataflow (concurrent signal assignments), behavioral (process statements), and structural (component instantiations). A single architecture may mix styles. 

architecture dataflow of half_adder is
begin
  sum   <= a xor b;
  carry <= a and b;
end architecture dataflow;

For sequential logic or designs requiring explicit control flow, a process statement is used instead. The process sensitivity list specifies which signal changes trigger re-evaluation 

architecture behavioral of half_adder is
begin
  process(a, b)  -- sensitivity list
  begin
    sum   <= a xor b;
    carry <= a and b;
  end process;
end architecture behavioral;

VHDL-Online notes that architectures include concurrent statements and may contain processes, signal assignments or component instantiations [4]. The declarative part may declare internal signals, type definitions or component declarations.

Components and Structural Design

Structural modelling builds a design from lower-level components. Components must first be declared and then instantiated within an architecture. For example, a full adder can be constructed from two half adders and an OR gate:

architecture structural of full_adder is 
-- declarative region: components AND internal signals go here 
component half_adder is 
      port (a, b : in std_logic; sum, carry : out std_logic); 
end component; 
component or_gate is 
     port (i1, i2 : in std_logic; y : out std_logic); 
end component; 
signal s1, c1, c2 : std_logic; 
begin 
ha1: half_adder port map(...); 
... 
end architecture structural; 

The component declarations are placed in the architecture's declarative region [4], and each instance is labeled. Component instantiation can use named or positional association [4]. Since VHDL-93, it's possible to instantiate entities directly without an explicit component declaration; however, many designers still use components for clarity.

Configurations

A configuration selects which architecture to pair with an entity and binds components to particular entity-architecture pairs. Without an explicit configuration, default binding applies: the component name must match a visible entity name in the target library, and the most recently compiled architecture for that entity is selected. This compile-order dependency is a common source of simulation inconsistencies in multi-architecture designs; explicit configurations are recommended wherever more than one architecture exists  [4]. Configurations provide a formal way to assemble design hierarchies for simulation or synthesis, especially when multiple architectures exist or vendor-specific components are used.

Packages and Libraries

Packages group related type declarations, constants, and subprograms so they can be shared across design units. A package consists of a declaration — which defines the public interface of types, constants, subprogram signatures, and component declarations — and an optional package body, which provides implementations for subprograms (functions and procedures) and completions for any deferred constants.  [4]. Packages are stored in libraries; the default library is work but standard packages are stored in IEEE. To use a package, designers write:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

Libraries are collections of compiled design units. The work library is the default target library and is always implicitly visible; all other libraries — including IEEE and vendor-specific libraries — must be made visible with an explicit library clause before use.  [4]. Many vendor tools provide additional libraries (e.g., UNISIM for AMD primitives).

Data Types and the IEEE 1164 Library

Bit and Boolean Types

At its core, VHDL defines simple scalar types such as bit (with values '0' and '1') and boolean. bit is an unresolved type; the VHDL elaborator raises an error if more than one driver is assigned to a signal of this type, regardless of whether the driven values agree. For realistic bus modelling, designers use the IEEE 1164 package to get multi-valued logic types.

std_ulogic and std_logic

The IEEE 1164 standard introduces std_ulogic, a nine-valued enumerated type with elements 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-' [2]. The std_logic type is defined as a resolved subtype of std_ulogic using a resolution function so that conflicting drivers can be reconciled [2]. The std_logic_vector type is an array of std_logic elements, commonly used for buses.

Using std_logic instead of bit enables simulation of tri-state buses and detection of multi-driver errors. The HDL Factory guide explains that unresolved signals such as std_ulogic cause an elaboration error when multiple drivers are present; the source compiles successfully but the design cannot be elaborated or simulated, while resolved signals rely on a resolution function to combine values [13]. Designers declare signals as std_logic or std_logic_vector by default to avoid such errors.

numeric_std and Numeric Types

The numeric_std package defines two array types, UNSIGNED and SIGNED, built on std_logic [3]. Both types treat the leftmost bit as the most significant bit and provide overloaded arithmetic operators (+, -, *) and the concatenation operator (&), along with comparison and type conversion functions  [3]. Because these types avoid vendor-specific packages (such as std_logic_unsigned), they are portable and synthesizable.

Integer subtypes (e.g., natural, positive, range-limited integer) are also part of VHDL. Prior to VHDL-2019, the standard required only a 32-bit signed integer range, though tools could optionally support wider ranges. VHDL-2019 formally mandates a minimum range of −(2⁶³) to (2⁶³)−1 for all compliant implementations [7].

Composite Types and Records

Arrays (std_logic_vector, UNSIGNED) and records allow grouping related signals. For example, a streaming interface can be defined as a record in VHDL-2019:

type streaming_bus is record
  data  : std_logic_vector(31 downto 0);
  valid : std_logic;
  ready : std_logic;
end record;

VHDL-2019 adds mode views to assign directions to record fields, enabling interface definitions independent of direction. Sigasi's article demonstrates using a streaming_master view to specify which fields are inputs or outputs [6]. Tool support for VHDL-2019 mode views varies by vendor; designers should verify support in their target toolchain before adopting this construct in production designs. 

Enumerated Types and Subtypes

Designers often create enumerated types for finite state machines:

type state_type is (idle, start, compute, finish);
subtype state_range is state_type range start to finish;
signal state : state_type := idle;

HDL's strong typing guarantees that only defined enumeration values can be assigned within the VHDL model; however, after synthesis, state encoding is represented in binary and the type-safety guarantee does not extend to the netlist.

Modelling Styles

Dataflow Style (Concurrent Signal Assignments)

In the dataflow style, hardware behavior is expressed using concurrent signal assignment statements. These assignments execute whenever their right-hand expressions change, enabling intuitive representation of combinational logic. Buzztech notes that dataflow descriptions directly show how data moves through the system [5]. The half-adder dataflow architecture above is a classic example.

Selected and conditional signal assignment statements (with/select and when/else) provide compact ways to implement multiplexers:

-- 2-to-1 multiplexer using with/select
with sel select
  y <= a when '0',
       b when others;

Sigasi recommends using process(all) in VHDL-2008 to avoid missing signals in the sensitivity list [6]. The case? pattern-matching construct introduced in VHDL-2008 allows grouping patterns with don't-care bits [6].

Behavioral Style (Processes)

Within a process, case provides the sequential equivalent of the concurrent with/select construct and is preferred for complex multi-branch combinational logic. 

In the behavioral style, designers use process blocks containing sequential statements. A process can model complex combinational logic or synchronous sequential logic. For sequential logic, processes typically use a clock edge and optional reset:

process(clk, rst)
begin
  if rst = '1' then
    q <= '0';
  elsif rising_edge(clk) then
    q <= d;
  end if;
end process;

Within a process, variables (:=) provide temporary storage and are updated immediately, while signals (<=) schedule updates at the end of the process. VHDL-Online notes that non-shared variables are scoped to the process or subprogram in which they are declared. VHDL-93 introduced shared variables, which are visible across all processes in an architecture but require careful use to avoid non-deterministic behaviour from simultaneous access and assignments take effect immediately [4]. Nandland summarises the key differences: signal assignments within a process are scheduled for the end of the current simulation cycle; if a signal is assigned multiple times within the same process activation, only the last assignment takes effect — earlier ones are overwritten, not queued  [12].

Structural Style (Component Instantiation)

Structural modelling uses component instantiation to build hierarchies. This style is indispensable when connecting existing IP cores or vendor primitives. Buzztech notes that structural descriptions are common for large systems where the behavior is best expressed as an interconnection of modules [5].

Concurrent vs Sequential Statements

VHDL mixes concurrent and sequential semantics. Concurrent statements (outside processes) execute in parallel; sequential statements (inside processes) execute in order. This distinction influences simulation and synthesis.

Processes and Sensitivity Lists

A process without a wait statement needs a sensitivity list. During simulation, the process wakes whenever any signal in the list changes. For combinational logic, the sensitivity list must contain all signals read within the process; otherwise simulation results can mismatch synthesis. VHDL-Online emphasises that missing a signal in the sensitivity list can lead to latches or incorrect behavior [4]. The VHDL-2008 process(all) form eliminates this risk by automatically including all read signals [6].

Signal vs Variable Semantics

Signals model wires and register outputs. Assigning to a signal schedules an update for the next delta cycle or clock edge. Variables are local to a process and update immediately. Confusing the two can cause simulation mismatches. Nandland demonstrates that multiple signal assignments within a process result in only the last assignment taking effect, while variable assignments accumulate [12].

Rising Edge Detection

Clocked processes should detect a specific edge. Industry coding guidelines strongly prefer rising_edge(clk) over clk'event and clk='1' because rising_edge() checks that the previous value was '0', preventing false triggering on transitions from 'X' or 'U'; clk'event and clk='1' fires on any transition to '1' regardless of the previous value. Both are supported by synthesis tools for flip-flop inference All major synthesis tools — Vivado, Quartus Prime, and Synopsys Design Compiler — infer flip-flops from both rising_edge(clk) and clk'event and clk='1'. However, the two are not simulation-equivalent: rising_edge(clk) returns true only on a '0'-to-'1' transition, while clk'event and clk='1' also fires on an 'X'-to-'1' transition, making it susceptible to false triggering on uninitialized clocks. Industry coding guidelines therefore prefer rising_edge() for all new designs; clk'event remains acceptable in legacy code 

Testbench Workflow and Verification Frameworks

A testbench is VHDL code that exercises the design under test (DUT). Testbenches are generally non-synthesizable: they may use wait statements, file I/O, randomization, and assert statements. The typical testbench architecture contains:

1. Stimulus generation: a process or procedure that drives inputs to the DUT.

2. DUT instantiation: the design unit under test.

3. Monitoring and checking: processes that compare outputs against expected values using assert statements.

Assertions provide run-time checks and improve coverage. Assert statements have supported severity levels (note, warning, error, failure). VHDL-2008 enhanced reporting capabilities and introduced the PSL-based assertion subset. VHDL-2019 introduced conditional analysis directives — a compile-time conditional compilation mechanism 

Modern verification frameworks build on these foundations:

1. OSVVM (Open Source VHDL Verification Methodology) offers a transaction-level verification framework, constrained random stimulus, functional coverage, scoreboards and memory models [14]. It emphasises readability and reusability of test cases and runs across all major simulators including GHDL, NVC, Siemens Questa, Synopsys VCS, Cadence Xcelium, Aldec Riviera-PRO, and Xilinx XSIM  The 2024 Wilson Research Group Verification Survey found OSVVM used by 35% of FPGA designers worldwide, making it the leading VHDL verification methodology globally. [14].

2. VUnit is an open-source unit testing framework for VHDL and SystemVerilog with a Python-based test runner that automates compilation order, testbench discovery, parallel execution, incremental compilation, logging, and built-in assertion packages. It imposes no specific verification methodology, complementing rather than replacing existing testbench approaches

Verification frameworks such as OSVVM and VUnit can contribute evidence toward DO-254 and ISO 26262 compliance by generating coverage metrics, structured test reports, and requirement traceability artefacts. However, full compliance with either standard requires additional tool qualification, independence of verification activities, and formal documentation processes beyond what a framework alone provides.

Recommended Reading:  FPGA Programming: Theory, Workflow, and Practical Implementations

Synthesis Tools and FPGA Targets

AMD Vivado

AMD Vivado Design Suite 2024.x supports extensive VHDL-2008 features. The official documentation lists support for matching relational operators (?=, ?/=) that return std_logic rather than boolean, maximum/minimum operators, shift and rotate operators for signed/unsigned types (rol, ror, sll, srl, sla, sra), unary logical reduction operators, and array-scalar logical operations [7]. Vivado also supports improved generate statements with elsif and else branches and pattern-matching case statements [7].

For VHDL-2019, Vivado 2024.x introduces VHDL-2019 features including record mode views (interfaces), conditional analysis tool directives, and 64-bit integers.  [7]. Tool support is evolving; designers should consult release notes to confirm which constructs are synthesizable.

Intel Quartus Prime

Quartus Prime Pro Edition synthesis supports IEEE VHDL standards 1987, 1993, 2008, and 2019. VHDL-2019 support includes conditional analysis tool directives; note that VHDL-2008 and VHDL-2019 feature coverage differs between the Pro and Standard editions, with Standard edition receiving more limited 2019 support  [8]. The Intel documentation lists specific VHDL-2008 constructs supported: unconstrained array elements, matching equality operators, condition operators, matching case statements, simplified sensitivity lists (process(all)), elsif/else in generate statements and enhanced bit-string literals [8]. 

Lattice Radiant and Diamond

Lattice's Radiant and Diamond design suites support VHDL-1993 and VHDL-2008 along with Verilog and SystemVerilog according to the vendor's feature table [9]. Lattice Radiant supports VHDL-1993 and VHDL-2008 for Nexus, ECP5, and CrossLink families whereas Lattice Diamond, used for older device families, supports VHDL-1993 with more limited VHDL-2008 coverage; designers should verify specific construct support against the Diamond synthesis documentation.

Microchip Libero SoC

Microchip's Libero SoC integrates Synopsys Synplify Pro for synthesis and Siemens ModelSim for simulation. The Microchip site notes that Synplify Pro supports the latest VHDL constructs including SystemVerilog and VHDL-2008 [10]. Therefore, designers targeting Microchip's PolarFire and RTG4 FPGAs can adopt most VHDL-2008 features.

Open-Source Tools: GHDL, Yosys and nextpnr

GHDL is an open-source VHDL compiler and simulator. GHDL v5.x (2025–2026) supports VHDL-2019 in partial form via the --std=19 flag; VHDL-2008 support via --std=08 is more complete. Designers should check the GHDL release notes for the specific version in use, as --std=19 feature coverage is actively expanding but not yet complete [11]. Earlier releases improved VHDL-2008 support and added an experimental synthesis kernel.

Yosys and the ghdl-yosys-plugin allow GHDL to act as a VHDL front end for open-source synthesis flows. Combined with nextpnr, these tools enable end-to-end FPGA implementation for some devices (e.g., Lattice iCE40, ECP5). However, VHDL-2019 synthesis support is still experimental.

Other Tools

Siemens Questa Prime/ModelSim and Synopsys VCS provide high-performance simulation environments. GHDL can also be used alongside commercial simulators in mixed-tool flows; OSVVM and VUnit both support GHDL as a simulator backend, enabling GHDL-based testbenches to participate in broader verification environments.

Common Pitfalls and Best Practices

Inferred Latches

In combinational processes, leaving out signal assignments for one or more branches causes the synthesiser to infer a latch to preserve the previous value. This pitfall does not apply to clocked processes, where unassigned signals resolve to registers.  AMD's synthesis guide warns that inferred latches are often the result of HDL coding mistakes, such as incomplete if or case statements [7]. Nandland illustrates the problem: missing an else branch in a process causes the previous value to be preserved, synthesizing a latch. The fix is to assign default values to signals and cover all branches [12]. Always include an else clause or assign a default at the start of the process.

Multi-Driven Nets and Resolution

Driving an unresolved signal, such as std_ulogic, from more than one concurrent source causes an elaboration error — the source analyses cleanly, but the design fails to elaborate. The HDL Factory guide explains that unresolved signals (like std_ulogic) cannot be driven by multiple sources; when multiple drivers attempt to assign a value, VHDL must resolve the conflict, or it is an error [13]. Use resolved types (std_logic) for shared buses and avoid unintended multi-driver scenarios by connecting only one driver or using a tri-state buffer pattern.

Signal vs Variable Confusion

Variables update immediately inside a process, while signals schedule updates. The most common variable misuse is reading a variable after assignment within the same process and expecting the pre-assignment value — variables update immediately, so the read reflects the new value. Designers expecting signal semantics (deferred update) must use signals instead. Nandland advises avoiding variables unless necessary and remembering that multiple signal assignments in a process only retain the last assignment [12].

Case Sensitivity and Identifiers

VHDL identifiers are generally case insensitive, meaning signal_a, Signal_A and SIGNAL_A refer to the same object [4]. VHDL-93 introduced extended identifiers delimited by single backslashes (e.g., \MySignal\), which are case sensitive and permit special characters and reserved words as identifiers. To include a literal backslash within an extended identifier, double it: \My\\Signal\.  [4]. Avoid mixing cases arbitrarily and use consistent naming conventions.

Tool-Specific Unsupported Features

Not all tools support every VHDL construct. For instance, pattern matching (case?) and interfaces may not synthesize in older versions of Vivado or Quartus. Always check vendor documentation and compile with warnings enabled. When targeting open-source flows, restrict code to well-supported VHDL-93/2008 constructs.

Modern VHDL Extensions

VHDL-2008 Highlights

The 2008 revision introduced many productivity features now widely supported:

• Matching relational operators (?=, ?/=, ?<, ?<=, ?>, ?>=) return the operand type rather than boolean — for std_logic and std_logic_vector operands this yields std_logic, enabling direct use in signal assignments without intermediate boolean conversion  [7].

• Maximum and minimum functions for scalar and array types [7].

• Overloaded shift and rotate operators (rol, ror, sll, srl, sla, sra) for signed and unsigned types in numeric_std — these operators existed since VHDL-1993 but were not overloaded for numeric_std types until 2008  [7].

• Unary reduction operators (and, or, nand, nor, xor, xnor) collapse a vector to a single std_ulogic value — note the return type is std_ulogic, not std_logic; an explicit conversion may be required when assigning to std_logic targets  [7].

• process(all) and wait on all semantics remove the need to list every signal in the sensitivity list [6].

• generate enhancements allow elsif and else branches and pattern-matching in case generates [7].

• Pattern matching in case? statements simplifies decoding with don't-care bits [6].

• Extended bit-string literals are supported in Quartus [8].

VHDL-2019 Features

The 2019 revision brings interface abstractions and improved usability:

• Interfaces using mode views: record types can define interfaces and views assign directions to fields. Sigasi shows examples of a streaming_bus record with a streaming_master view that specifies which fields are inputs or outputs [6]. This reduces port-mapping verbosity and improves reuse.

• Conditional analysis tool directives with user-defined and tool-defined conditional identifiers — a compile-time conditional compilation mechanism analogous to #ifdef in C, enabling portable code that adapts to different tools and device targets 

• Implicitly 64-bit integers: all integers are at least 64 bits [7].

• Simplified assignment from arrays to scalars and other minor improvements.

Tool support for VHDL-2019 is still in progress: Vivado supports interface definitions and 64-bit integers [7], while GHDL provides experimental simulation with the --std=19 flag [11].

Emerging Trends: Python-Based HDLs and AI-Assisted RTL

While VHDL and Verilog remain dominant, alternative HDLs are gaining traction. Tools like MyHDL allow writing synthesizable RTL in Python, converting to Verilog or VHDL for standard tool flows. Cocotb is a separate Python-based verification framework that drives HDL simulations via coroutines — it is not a design language and produces no synthesizable output   AI-assisted RTL generation has advanced beyond skeleton code suggestion — current tools from Cadence, Synopsys, and open-source LLM-based flows can generate synthesisable RTL blocks from natural language specifications, assist with formal property generation, and automate repetitive structural patterns. Adoption in safety-critical domains remains limited pending tool qualification frameworks, but the technology is in active production use in commercial semiconductor design. However, rigorous verification and adherence to standards are still required in safety-critical domains.

Conclusion

VHDL's enduring relevance stems from its strong typing, deterministic semantics and alignment with safety-critical design philosophies. The language's design units (entities, architectures, configurations and packages) provide a structured approach to hardware description, while the IEEE 1164 and numeric_std libraries furnish robust data types. Understanding the difference between concurrent signal assignments and sequential processes, along with proper use of sensitivity lists, prevents common pitfalls such as inferred latches and unintended multi-driver nets. Modern verification frameworks like OSVVM and VUnit complement VHDL's robust type system by automating testbench creation, coverage and reporting.

Vendor toolchains now broadly support VHDL-2008 and are steadily adopting VHDL-2019 features. Whether you are targeting AMD Vivado, Intel Quartus, Lattice Radiant, Microchip Libero or an open-source flow with GHDL and Yosys, familiarity with the supported feature set is essential. Despite the growing popularity of SystemVerilog for verification, VHDL remains a first-class choice for FPGA and ASIC synthesis — and the mandated or preferred language in DO-254 avionics, ISO 26262 automotive, and MIL-STD defense programmes where determinism and traceability are compliance requirements .

FAQ

What is VHDL used for?

VHDL is a hardware description language used to model, simulate and synthesize digital circuits. Engineers write VHDL to describe the behavior and structure of FPGAs, ASICs. .. Mixed-signal systems require VHDL-AMS (IEEE 1076.1-2017), a separate analog and mixed-signal extension of the base standard. The language supports multiple levels of abstraction, from gate-level netlists to algorithmic behavioral models, making it suitable for designing processors, communications interfaces, control logic and safety-critical avionics. Its strong typing and deterministic semantics make it popular in aerospace, defense and automotive industries [1].

VHDL vs Verilog: which should I learn first?

The choice depends on your goals. VHDL is strongly typed and verbose, enforcing explicitness and catching errors early [1]. It is widely used in European and safety-critical FPGA projects. Verilog and its successor SystemVerilog have a C-like syntax, are more concise, and dominate ASIC design and verification. Many engineers learn both VHDL for synthesis and SystemVerilog for verification. If you plan to work in aerospace or defense, learning VHDL first can provide advantages in compliance and determinism.

Is VHDL still used in 2026?

Yes. Most FPGA vendors and synthesis tools continue to support VHDL-2008, and vendors like AMD and GHDL are adopting VHDL-2019 features [7][11]. Aerospace, defense and automotive industries rely heavily on VHDL due to its traceability and strong typing. Even as SystemVerilog grows, VHDL remains the primary design language for many safety-critical and legacy projects.

What is the difference between std_logic and bit?

bit is an unresolved type with only '0' and '1'. bit is an unresolved type; the VHDL elaborator raises an error if more than one driver is assigned to a bit signal, regardless of whether the driven values agree. The IEEE 1164 package defines std_ulogic and std_logic. std_logic is a resolved subtype of std_ulogic with nine values ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-') [2]. Because std_logic has an associated resolution function, it can represent tri-state buses and detect multi-driver conflicts.

What does the library IEEE statement do?

The library IEEE; use IEEE.std_logic_1164.all; statements make the contents of the IEEE library and the std_logic_1164 package available in the current design unit. VHDL compilers store compiled units in libraries; the default is work. IEEE packages must be explicitly made visible using the library and use clauses [4]. Without them, types like std_logic and functions like rising_edge are undefined.

Can VHDL be used to design ASICs?

Yes. Although FPGAs are common, VHDL is equally applicable to ASIC design. Many ASIC synthesis tools accept VHDL and convert it into gate-level netlists. However, some ASIC flows prefer SystemVerilog for verification and design. When designing ASICs, ensure that your VHDL code adheres to synthesizable constructs and that your foundry's libraries support the required features.

What is the difference between a signal and a variable in VHDL?

Signals model physical wires; assignments to signals schedule updates that take effect after a simulation delta cycle or clock edge. Non-shared variables are scoped to the enclosing process or subprogram. VHDL-93 introduced shared variables, which are visible across all processes in an architecture but require careful use to avoid non-deterministic behaviour from simultaneous access.  Variable assignments take effect immediately upon execution.  Multiple signal assignments in a process are superseded by later ones — only the last scheduled value takes effect at process suspension  [12]. Use signals for communication between processes and variables for intermediate combinational calculations within a process.

What is a testbench in VHDL?

A testbench is VHDL code that instantiates the design under test and provides stimulus, monitors outputs and checks correctness. Testbenches use non-synthesizable constructs including wait statements and file I/O, and may employ constrained-random stimulus via framework packages such as OSVVM's RandomPkg. Modern verification frameworks — OSVVM, VUnit, and UVVM — complement VHDL's robust type system by automating testbench creation, coverage collection, and structured reporting  [14][15]. A well-constructed testbench is critical for verifying functionality before synthesis and hardware deployment.

What is a VHDL entity?

A VHDL entity defines the external interface of a hardware block — its port names, directions (in, out, inout, buffer), and data types. The entity contains no implementation; that is provided by a separate architecture. Together, entity and architecture form the fundamental VHDL design unit used in every FPGA and ASIC design.

What is the difference between VHDL-2008 and VHDL-2019?

VHDL-2008 (IEEE 1076-2008) introduced matching operators, process(all), and enhanced generate statements, now broadly supported by Vivado and Quartus. VHDL-2019 (IEEE 1076-2019) adds record mode views for interface abstraction, conditional analysis tool directives for portable code, and mandates 64-bit integer ranges. Tool support for VHDL-2019 is still emerging as of 2025–2026.

References

[1] B. Butka, "Advanced Verification Methods for Safety-Critical Airborne Electronic Hardware," Federal Aviation Administration, Tech. Rep. DOT/FAA/TC-14/41, 2015. [Online]. Available: https://www.faa.gov/sites/faa.gov/files/aircraft/air_cert/design_approvals/air_software/TC-14-41.pdf

[2] IEEE Model Standards Group, "std_logic_1164 Multi-Value Logic System," UMBC VHDL Package Repository. [Online]. Available: https://portal.cs.umbc.edu/help/VHDL/packages/std_logic_1164.vhd

[3] IEEE Model Standards Group, "numeric_std VHDL Package," UMBC VHDL Package Repository. [Online]. Available: https://portal.cs.umbc.edu/help/VHDL/stdpkg.html

[4] B. Mealy and F. Tappero, Free Range VHDL, 2012. [Online]. Available: https://github.com/fabriziotappero/Free-Range-VHDL-book/raw/master/free_range_vhdl.pdf

[5] IEEE Standards Association, "IEEE Std 1076-2019 — IEEE Standard for VHDL Language Reference Manual," IEEE, Dec. 2019. [Online]. Available: https://ieeexplore.ieee.org/document/8938196

[6] Sigasi NV, "VHDL Design Articles — Signal Assignments, Pattern Matching, and VHDL-2019 Mode Views," Sigasi. [Online]. Available: https://www.sigasi.com/tech/

[7] AMD Inc., "Vivado Design Suite User Guide: Synthesis (UG901), VHDL-2008 Language Support," AMD, 2025. [Online]. Available: https://docs.amd.com/r/en-US/ug901-vivado-synthesis/VHDL-2008-Language-Support

[8] Intel Corporation, "Intel Quartus Prime Support for VHDL 2008," Intel. [Online]. Available: https://www.intel.com/content/www/us/en/programmable/quartushelp/22.4/hdl/vhdl/vhdl_list_2008_vhdl_support.htm

[8b] Intel Corporation, "Intel Quartus Prime Support for VHDL 2019," Intel. [Online]. Available: https://www.intel.com/content/www/us/en/programmable/quartushelp/21.3/hdl/vhdl/vhdl_list_2019_vhdl_support.htm

[9] Lattice Semiconductor, "Lattice Radiant Software User Guide," Lattice Semiconductor Corporation, 2021. [Online]. Available: https://www.latticesemi.com/-/media/LatticeSemi/Documents/Radiant31/Radiant31_User_Guide.ashx?document_id=53415

[10] Microchip Technology Inc., "Libero SoC Design Suite — Synthesis and Simulation," Microchip Technology. [Online]. Available: https://www.microchip.com/en-us/products/fpgas-and-plds/fpga-and-soc-design-tools/fpga/libero-software-later-versions

[11] GHDL Contributors, "GHDL — Open Source VHDL Simulator and Compiler," GHDL Project. [Online]. Available: https://ghdl.github.io/ghdl/

[12a] R. Nandlall, "How to Avoid Creating a Latch in VHDL," Nandland. [Online]. Available: https://nandland.com/how-to-avoid-creating-a-latch/

[12b] R. Nandlall, "Variables vs. Signals in VHDL," Nandland. [Online]. Available: https://nandland.com/variables-vs-signals/

[13] IEEE, "IEEE Std 1164-1993 — IEEE Standard Multivalue Logic System for VHDL Model Interoperability," IEEE, 1993. [Online]. Available: https://ieeexplore.ieee.org/document/392561

[14] OSVVM Contributors, "OSVVM — Open Source VHDL Verification Methodology," OSVVM Project. [Online]. Available: https://osvvm.github.io/

[15] VUnit Contributors, "VUnit — Unit Testing Framework for VHDL and SystemVerilog," VUnit Project. [Online]. Available: https://vunit.github.io/