<h2 id="isPasted">What was announced</h2>OmniOn Power, a power conversion manufacturer, announced four QODN bus converters as the second generation of its Osprey family: non-isolated, regulated modules that convert a 40 to 60 V rack supply to a 12 V intermediate bus.[1][2] The QODN108, QODN136, QODN167 and QODN217 deliver 1.3, 1.6, 2.0 and 2.6 kW in a 58.4 × 36.8 × 14.5 mm quarter brick, the same outline as the first-generation QODE modules launched in February 2025, which stopped at 2 kW. OmniOn claims a peak efficiency of up to 98.5%, "high, flat efficiency curves across their operating band", and up to 1% better efficiency than the QODE generation.[1][3]<h2>Why it matters</h2>The 2 kW QODN167 reaches a typical 98.0% at 54 V input, full load and 25 °C ambient, against 97.1% for the first-generation QODE167. Our calculation (loss = output power × (1/efficiency - 1)) puts dissipation at about 41 W for the QODN167 and 60 W for the QODE167, about 32% less. The QODN136 and QODN108 come out about 30% and 33% below the QODE136 and QODE108. At 20% load and 54 V the QODN167 curve reads about 97.5% against the QODE167's 96.2%, a wider gap.[4][5][6][7][8][9]The 2.6 kW QODN217, at a typical 97.8% at 54 V and full load, dissipates about 58 W by the same calculation, close to the QODE167's 60 W. Derating curves agree: with a 25.4 mm high heatsink and about 3 m/s airflow at 54 V, the QODE167, QODN167 and QODN217 hold full current to roughly 46 °C, 65 °C and 47 °C ambient respectively.[2][4][5]Flex Power Modules' BMR352, a competing regulated, non-isolated quarter brick announced in November 2024, is rated 2 kW continuous in the same outline, at a typical 97.5% at 54 V and full load, specified at a 25 °C module reference temperature where OmniOn uses 25 °C ambient. Advanced Energy's NDQ1600, a 1.6 kW module of the same type launched in August 2025, reaches 96.8% at full load and 50 V input.[10][11][12][13]All four QODN models are most efficient at 51 V, then 54 V, among the 40, 51, 54 and 60 V curves OmniOn plots, over most of the load range. Those are the two nominal power shelf outputs in the Open Compute Project's Open Rack V3 (ORv3) specification.[14] At the 40 V minimum and full load, the QODN167's typical efficiency falls to about 95.8%, below roughly 97.5% for the QODE167 and 97.9% for Flex's BMR352. The QODN217 falls to about 94.7%, about 143 W on OmniOn's dissipation plot.[2][4][5][6][8][11]<h2 id="isPasted">Technical specifications: OmniOn Power QODN Osprey bus converters (2nd generation), by model. </h2>Full part numbers add the suffix A0B.<div><table><thead><tr><th>Spec</th><th>QODN108</th><th>QODN136</th><th>QODN167</th><th>QODN217</th></tr></thead><tbody><tr><td>Continuous output power</td><td>1300 W</td><td>1600 W</td><td>2000 W</td><td>2600 W</td></tr><tr><td>Rated output current</td><td>108 A</td><td>136 A</td><td>167 A</td><td>217 A</td></tr><tr><td>Input voltage</td><td>40 to 60 V (54 V nominal)</td><td>40 to 60 V (54 V nominal)</td><td>40 to 60 V (54 V nominal)</td><td>40 to 60 V (54 V nominal)</td></tr><tr><td>Output voltage</td><td>12.0 V regulated, 9.5 to 12.5 V programmable</td><td>12.0 V regulated, 9.5 to 12.5 V programmable</td><td>12.0 V regulated, 9.5 to 12.5 V programmable</td><td>12.0 V regulated, 9.5 to 12.5 V programmable</td></tr><tr><td>Isolation</td><td>Non-isolated</td><td>Non-isolated</td><td>Non-isolated</td><td>Non-isolated</td></tr><tr><td>Footprint</td><td>Modified DOSA digital quarter brick</td><td>Modified DOSA digital quarter brick</td><td>Modified DOSA digital quarter brick</td><td>Modified DOSA digital quarter brick</td></tr><tr><td>Converter topology</td><td>not stated in datasheet</td><td>not stated in datasheet</td><td>not stated in datasheet</td><td>not stated in datasheet</td></tr><tr><td>Efficiency, full load, 54 V in, 25 °C ambient (typical)</td><td>98.1%</td><td>98.1%</td><td>98.0%</td><td>97.8%</td></tr><tr><td>Efficiency, full load, 51 V in, 25 °C ambient (typical)</td><td>98.2%</td><td>98.2%</td><td>98.1%</td><td>97.9%</td></tr><tr><td>Highest tabulated efficiency, 51 V in, 25 °C ambient (typical)</td><td>98.4% at 60% load</td><td>98.5% at 60% load</td><td>98.5% at 60% load</td><td>98.5% at 50% load</td></tr><tr><td>Guaranteed minimum efficiency</td><td>not stated</td><td>not stated</td><td>not stated</td><td>not stated</td></tr><tr><td>Surge output power</td><td>1800 W for 70 ms in a 400 ms period</td><td>2400 W for 3 ms in a 16 ms period (40 to 48 V in) or 70 ms in a 400 ms period (48 to 60 V in)</td><td>3000 W for 3 ms in a 16 ms period (45 to 60 V in)</td><td>4000 W for 3 ms in a 16 ms period (45 to 60 V in)</td></tr><tr><td>Switching frequency</td><td>140 kHz</td><td>140 kHz</td><td>140 kHz</td><td>140 kHz</td></tr><tr><td>Maximum input fuse</td><td>40 A</td><td>40 A</td><td>80 A</td><td>80 A</td></tr><tr><td>Thermal limit</td><td>95 °C at reference point TH1</td><td>95 °C at reference point TH1</td><td>95 °C at reference point TH1</td><td>95 °C at reference point TH1</td></tr><tr><td>Operating ambient</td><td>-40 to +85 °C, with current derating</td><td>-40 to +85 °C, with current derating</td><td>-40 to +85 °C, with current derating</td><td>-40 to +85 °C, with current derating</td></tr><tr><td>Dimensions (standard height)</td><td>58.4 × 36.8 × 14.5 mm</td><td>58.4 × 36.8 × 14.5 mm</td><td>58.4 × 36.8 × 14.5 mm</td><td>58.4 × 36.8 × 14.5 mm</td></tr><tr><td>Weight with base plate</td><td>85.8 g</td><td>86.6 g</td><td>90 g</td><td>90 g</td></tr><tr><td>Digital interface</td><td>PMBus, subset of the 1.2 command set</td><td>PMBus, subset of the 1.2 command set</td><td>PMBus, subset of the 1.2 command set</td><td>PMBus, subset of the 1.2 command set</td></tr><tr><td>IPC-9592 compliance as listed</td><td>Category 2, Class I</td><td>Category 2, class not stated</td><td>Category 2, Class I</td><td>Category 2, Class I</td></tr><tr><td>Calculated MTBF (Telcordia SR-332, 80% load, Tc 40 °C, about 1 m/s airflow)</td><td>5.78 million h (Issue 3)</td><td>5.68 million h (Issue 4)</td><td>4.99 million h (Issue 4)</td><td>4.05 million h (Issue 3)</td></tr></tbody></table></div>Sources: [2][4][6][8][15]With a 25.4 mm high heatsink and about 3 m/s airflow at 54 V input, the QODN217 delivers roughly 120 A at 85 °C ambient. The QODN datasheets plot derating only at 51 V and 54 V input, so thermal behavior between 46 and 50 V, the lower part of the tolerance band for ORv3's 51 V option, has to be estimated or measured.[2][4][6][8][14] The QODN167 keeps the QODE167's pin assignment but needs twice the minimum external input capacitance (2 × 330 µF). The QODN217, QODN167 and QODN108 datasheets list IPC-9592 Class I where the QODE167 and QODE136 list Class II, and the QODN parts' calculated MTBF is lower at each shared rating.[2][4][5][6][7][8][9] <h2>References</h2><ol><li><a href="https://www.businesswire.com/news/home/20261001538548/en/OmniOn-Powers-Next-Generation-Osprey-Bus-Converters-Provide-High-Flat-Efficiency-for-AI-Data-Center-Applications">OmniOn Power's Next-Generation Osprey Bus Converters Provide High, Flat Efficiency for AI Data Center Applications</a>, Business Wire, 1 October 2026</li><li><a href="https://www.omnionpower.com/assets/pdfs/windchill/data-sheet/qodn217a0b_ds.pdf">QODN217A0B: Osprey Series DC-DC Converter</a>, OmniOn Power, 30 July 2026. Manufacturer datasheet, revision 3.46.</li><li><a href="https://www.omnionpower.com/about/news/press-releases/omnion-power-introduces-new-osprey-series-non-isolated-bus-converters-for-ai-server-applications">OmniOn Power Introduces New Osprey-Series Non-Isolated Bus Converters for AI Server Applications</a>, OmniOn Power, 27 February 2025</li><li><a href="https://www.omnionpower.com/assets/pdfs/windchill/data-sheet/qodn167a0b_ds.pdf">QODN167A0B: Osprey Series DC-DC Converter</a>, OmniOn Power, 5 August 2026. Manufacturer datasheet, revision 3.28.</li><li><a href="https://www.omnionpower.com/assets/pdfs/windchill/data-sheet/qode167a0b_ds.pdf">QODE167A0B: Osprey Series DC-DC Converter</a>, OmniOn Power, 3 August 2026. Manufacturer datasheet, revision 1.16, first generation.</li><li><a href="https://www.omnionpower.com/assets/pdfs/windchill/data-sheet/qodn136a0b_ds.pdf">QODN136A0B: Osprey Series DC-DC Converter</a>, OmniOn Power, 5 August 2026. Manufacturer datasheet, revision 1.37.</li><li><a href="https://www.omnionpower.com/assets/pdfs/windchill/data-sheet/qode136a0b_ds.pdf">QODE136A0B: Osprey Series DC-DC Converter</a>, OmniOn Power, 29 July 2026. Manufacturer datasheet, revision 1.8, first generation.</li><li><a href="https://www.omnionpower.com/assets/pdfs/windchill/data-sheet/qodn108a0b_ds.pdf">QODN108A0B: Osprey Series DC-DC Converter</a>, OmniOn Power, 29 July 2026. Manufacturer datasheet, revision 2.19.</li><li><a href="https://www.omnionpower.com/assets/pdfs/windchill/data-sheet/qode108a0b_ds.pdf">QODE108A0B: Osprey Series DC-DC Converter</a>, OmniOn Power, 29 July 2026. Manufacturer datasheet, revision 2.0, first generation.</li><li><a href="https://flex.com/resources/bmr352-delivers-unmatched-power-density-for-ai-data-centers/">BMR352 delivers unmatched power density</a>, Flex Power Modules, 6 November 2024</li><li><a href="https://flex.com/wp-content/uploads/2025/11/Datasheet-BMR352_C1.pdf">Datasheet BMR352 2200/031: 2000 W digital quarter brick DC/DC IBC</a>, Flex Power Modules, 3 July 2025</li><li><a href="https://www.advancedenergy.com/en-us/about/news/press/advanced-energy-launches-1300-and-1600-w-ultra-efficient-dc-dc-converter/">Advanced Energy Launches 1300 and 1600 W Ultra Efficient DC-DC Converter</a>, Advanced Energy, 27 August 2025</li><li><a href="https://www.advancedenergy.com/getmedia/3575736a-36e1-4992-9034-f76eafb6af2a/en-datasheet-NDQ1600-07-25.pdf">Artesyn NDQ1600 Series 1600W Quarter-Brick DC-DC Converter</a>, Advanced Energy, 25 July 2025. Manufacturer datasheet.</li><li><a href="https://www.opencompute.org/documents/open-rack-base-specification-version-3-pdf">Open Rack V3 Base Specification, Revision 1.0</a>, Open Compute Project, 22 September 2022. Section 12.1.</li><li><a href="https://www.digikey.com/en/product-highlight/o/omnion-power/osprey-bus-converters">Osprey Bus Converters, OmniOn Power</a>, DigiKey, accessed 5 October 2026. Distributor listing; stock and prices change.</li></ol>

OmniOn Power's new Osprey bus converters dissipate about 30% less at 54 V input and full load. Applications include data centers and high-density computing, distributed power architectures, and 12V intermediate bus applications.

Second-generation 48V-to-12V bus converters cut full-load losses

NTC Thermistor Soldered onto a Green Printed Circuit Board

Read what a thermistor is, how NTC and PTC types work, the beta and Steinhart-Hart equations, key specs, applications and how to test one.

Thermistor: How It Works, Types, Equations and Uses

<h2 id="isPasted">What is the announcement</h2>Toshiba Electronic Devices &amp; Storage Corporation <a href="https://www.businesswire.com/news/home/20260930980943/en/Toshiba-Launches-Dual-Channel-Standard-Digital-Isolators-that-Contribute-to-Lower-Power-Consumption-in-Industrial-Equipment">announced the DCL32xx00</a> series on 1 October 2026: four dual-channel digital isolators for industrial equipment. Toshiba says the DCL32xx00 draws 0.2 mA per channel (typical) at 1 Mbps and carries data at up to 25 Mbps.[1]The DCL320C00 and DCL320D00 have two channels in the same direction. The DCL321C00 and DCL321D00 have one channel each way, the arrangement a UART link needs. The C00 and D00 suffixes set the default output state, low or high. All four use magnetic coupling, are rated for 3,000 Vrms isolation, run from 2.25 V to 5.5 V between -40 °C and 125 °C, and come in an 8-pin narrow SOIC package.[1]<h2 id="isPasted">Why does it matter</h2>The DCL32xx00 is the two-channel version of the quad-channel DCL34xx0B series that Toshiba introduced in mid-2026, with the same per-channel current, data rate and timing.[2][3][4] Toshiba  described the technique in the DCL341x0B, the first DCL34xx0B parts, as a proprietary edge transmission method.[4] Edge-based schemes signal across the isolation barrier when the input changes state, so supply current falls with the data rate.[5][6] Toshiba's 150 Mbps DCL54x01 isolators use on-off keying, where a carrier crosses the barrier for as long as the input holds one logic state, an approach that draws more supply current at low data rates.[5][7]At 1 Mbps and 3.3 V, the DCL320C00 draws 0.16 mA and 0.26 mA on its two supplies. The DCL520C00, Toshiba's 150 Mbps dual-channel isolator in the same package and pinout, draws 5.7 mA and 2.7 mA, about 20 times more per channel (calculated from the datasheet figures). At 25 Mbps the DCL320C00 draws 3.1 mA per channel against about 5 mA for the DCL520C00. The DCL32xx00 gives up speed and transient immunity in exchange: its guaranteed common-mode transient immunity (CMTI) is 30 kV/µs against 100 kV/µs for the DCL52xx00 series, and its maximum propagation delay at 3.3 V is 52 ns against 19.1 ns.[2][8]<a href="https://www.ti.com/product/ISO7021" target="_blank" rel="noopener noreferrer">Texas Instruments' ISO7021</a>, a two-channel isolator with one channel each way, draws 120 µA per channel at 1 Mbps and 3.3 V with no load, where the DCL32xx00 draws about 180 µA. At rest the ISO7021 needs 4.8 µA per channel against roughly 130 µA for the DCL32xx00, but the ISO7021 tops out at 4 Mbps.[2][6] In the same 25 Mbps class, <a href="https://www.analog.com/en/products/max12930.html">Analog Devices' MAX12930</a>, a two-channel 3,000 Vrms isolator in a narrow SOIC, draws 0.39 mA per channel at 2 Mbps and 0.91 mA at 25 Mbps (3.3 V, no load, calculated from the datasheet figures). The DCL320C00's 3.1 mA at 25 Mbps includes a 15 pF load on each output.[2][9]<h2>Technical specifications, Toshiba DCL32xx00 series (DCL320C00, DCL320D00, DCL321C00, DCL321D00)</h2><div><table><thead><tr><th>Specification</th><th>Value</th></tr></thead><tbody><tr><td>Channels (forward:reverse)</td><td>DCL320C00, DCL320D00: 2:0. DCL321C00, DCL321D00: 1:1</td></tr><tr><td>Default output</td><td>C00 parts: low. D00 parts: high</td></tr><tr><td>Maximum data rate</td><td>25 Mbps (2.25 V to 5.5 V, -40 °C to 125 °C)</td></tr><tr><td>Supply current at 1 Mbps, 3.3 V (typ., 15 pF load, 25 °C)</td><td>DCL320x00: 160 µA (IDD1), 260 µA (IDD2). DCL321x00: 215 µA per side</td></tr><tr><td>Supply current at 1 Mbps, 5 V (typ., 15 pF load)</td><td>DCL320x00: 225 µA (IDD1), 375 µA (IDD2). DCL321x00: 305 µA per side</td></tr><tr><td>Supply current at 25 Mbps, 3.3 V (typ., 15 pF load)</td><td>DCL320x00: 3.4 mA (IDD1), 2.8 mA (IDD2). DCL321x00: 3.2 mA per side</td></tr><tr><td>Quiescent supply current, 3.3 V (typ.)</td><td>DCL320x00: 110 µA (IDD1), 155 µA (IDD2). DCL321x00: 135 µA per side</td></tr><tr><td>Propagation delay</td><td>3.3 V: 38 ns typ., 52 ns max. 5 V: 33 ns typ., 46 ns max. 2.5 V: 46 ns typ., 63 ns max.</td></tr><tr><td>Pulse width distortion (max.)</td><td>8 ns up to 10 Mbps, 13 ns up to 25 Mbps</td></tr><tr><td>CMTI</td><td>30 kV/µs min. (VCM = 400 V, 25 °C)</td></tr><tr><td>Isolation voltage</td><td>3,000 Vrms for 60 s (UL 1577)</td></tr><tr><td>Maximum repetitive peak isolation voltage (VIORM)</td><td>566 Vpk</td></tr><tr><td>Maximum surge isolation voltage (VIOSM)</td><td>5,200 Vpk</td></tr><tr><td>External creepage and clearance</td><td>3.8 mm</td></tr><tr><td>Supply voltage</td><td>2.25 V to 5.5 V</td></tr><tr><td>Operating temperature</td><td>-40 °C to 125 °C</td></tr><tr><td>Package</td><td>SOIC8-N, 4.9 × 6.0 mm, 1.75 mm maximum height</td></tr><tr><td>Safety approvals</td><td>UL 1577 and cUL approved. VDE 0884-17 and CQC listed as planned</td></tr><tr><td>Price</td><td>not stated</td></tr></tbody></table></div>Sources: [1][2]The 0.2 mA figure is a typical value at 3.3 V and 25 °C with a 15 pF load, averaged across both supplies. At 5 V the same sum gives 0.3 mA per channel, and the 3.3 V datasheet maximums give 0.42 mA.[2] Each channel carries signals one way only. Toshiba's release names I2C as a use for the DCL320C00 and DCL320D00, but I2C needs a bidirectional channel, and standard unidirectional isolators provide one only with external components.[1][10] The DCL52xx00 datasheet describes reinforced insulation with a 10,000 Vpk surge rating. The DCL32xx00 is rated at 5,200 Vpk, so the two families share a pinout but differ on insulation.[2][8]Recommended Reading:<a href="https://www.wevolver.com/article/gate-driver-design-for-modern-power-electronics"> Gate Driver Design for Modern Power Electronics</a>. Compares optocoupler, capacitive and magnetic isolation and explains why CMTI matters next to fast-switching power stages.<h2>References</h2><ol><li><a href="https://toshiba.semicon-storage.com/ap-en/company/news/news-topics/2026/10/isolators-solid-state-relays-20261001-1.html">Toshiba Launches Dual-Channel Standard Digital Isolators that Contribute to Lower Power Consumption in Industrial Equipment</a>, Toshiba Electronic Devices &amp; Storage Corporation, 1 October 2026. Press release.</li><li><a href="https://toshiba.semicon-storage.com/info/docget.jsp?did=169677&amp;prodName=DCL320C00">DCL320C00, DCL320D00, DCL321C00, DCL321D00 data sheet, Rev. 1.8</a>, Toshiba Electronic Devices &amp; Storage Corporation, 8 September 2026.</li><li><a href="https://toshiba.semicon-storage.com/info/docget.jsp?did=169045&amp;prodName=DCL341L0B">DCL34xx0B low power quad channel digital isolators data sheet, Rev. 1.6</a>, Toshiba Electronic Devices &amp; Storage Corporation, 8 September 2026.</li><li><a href="https://toshiba.semicon-storage.com/eu/company/news/2026/06/isolators-solid-state-relays-20260616-1.html">Toshiba augments standard digital isolator portfolio with two quad-channel, low power devices</a>, Toshiba Electronics Europe, 16 June 2026. Press release.</li><li><a href="https://www.analog.com/en/resources/technical-articles/the-use-of-robust-digital-isolators-in-the-harsh-environments.html">The Use of Robust Digital Isolators in the Harsh Environments of Electric Motor Drives</a>, Analog Devices, 1 August 2016. Vendor technical article comparing isolator architectures, not tied to this product.</li><li><a href="https://www.ti.com/lit/gpn/ISO7021" target="_self">ISO7021 Ultra-Low Power Two-Channel Digital Isolator data sheet, SLLSFA0C</a>, Texas Instruments, July 2019, revised May 2024.</li><li><a href="https://toshiba.semicon-storage.com/info/docget.jsp?did=105611&amp;prodName=DCL520C00">Basics of the Standard Digital Isolators, Rev. 1.2</a>, Toshiba Electronic Devices &amp; Storage Corporation, 10 April 2023. Application note covering the DCL54x01 series.</li><li><a href="https://toshiba.semicon-storage.com/info/docget.jsp?did=159485&amp;prodName=DCL520C00">DCL520C00, DCL520D00, DCL521C00, DCL521D00 data sheet, Rev. 1.4</a>, Toshiba Electronic Devices &amp; Storage Corporation, 8 September 2026.</li><li><a href="https://www.analog.com/media/en/technical-documentation/data-sheets/MAX12930-MAX12931.pdf">MAX12930/MAX12931 Two-Channel, Low-Power, 3kVRMS and 5kVRMS Digital Isolators data sheet, 19-8563 Rev. 10</a>, Analog Devices, August 2021.</li><li><a href="https://www.ti.com/document-viewer/lit/html/SSZT517/GUID-F7D0C00F-259C-4A0D-A56B-0D841B158D96">Top 6 Design Questions about I2C Isolators, SSZT517</a>, Texas Instruments, March 2019. Vendor technical article.</li></ol>

Toshiba Dual-Channel Standard Digital Isolator

Toshiba's four DCL32xx00 isolators trade speed and transient immunity for lower supply current.

New Dual-Channel Standard Digital Isolators for Industrial Equipment

<h2 id="isPasted">What was announced</h2><a href="https://www.dwavequantum.com/" target="_blank" rel="noopener noreferrer">D-Wave Quantum</a> launched a beta program on 1 October 2026 for its gate-model quantum computing simulator, a classical emulator announced in June 2026 and built around its dual-rail superconducting qubit technology. Select customers get access through D-Wave's Leap quantum cloud service and Ocean software development kit ahead of general availability. Named participants are the bank BBVA, FirstQFM (which builds foundation models for quantum computing), <a href="https://www.fau.edu/engineering/news/0127-onsite-quantum-computer/">Florida Atlantic University</a> and the <a href="https://www.fz-juelich.de/en/jsc" target="_blank" rel="noopener noreferrer">Jülich Supercomputing Centre</a>. D-Wave says the dual-rail design uses error detection to deliver error correction with "significantly lower hardware overhead as systems scale." The technology comes from Quantum Circuits Inc., a dual-rail qubit developer co-founded by Yale professor Rob Schoelkopf, which D-Wave acquired in January 2026.[1][2][3][4]<h2 id="isPasted">Why it matters</h2>A dual-rail cavity qubit stores one microwave photon shared between two superconducting cavities. Photon loss, the dominant error, leaves both cavities empty: a state outside the code space, detectable without disturbing the logical state. Errors at known locations are erasures, and a code of given distance corrects roughly twice as many of them as errors at unknown locations.[5][6]The simulator exposes this to programmers. In QCDL, D-Wave's Python-embedded circuit language, a measurement returns 0, 1 or *, where * marks a qubit detected outside the code space. A non-destructive mced() instruction checks for erasure mid-circuit, conditional blocks can branch on the result, and jobs can post-select erasure-free shots. The simulator's noisy mode applies Pauli errors, leakage and seepage (return into the code space) after gates and idle periods.[7][8]<img src="https://s3-us-west-1.amazonaws.com/wevolver-project-images/froala%2F1790934344026-Screenshot+2026-10-02+at+10-10-59+D-Wave+Quantum+Simulator+-+Future+Access+Request.png" style="width:100%px" class="fr-fic fr-dib" />D-Wave Quantum ChipD-Wave ties the simulator to a controlled-Z (CZ) gate its researchers reported in Nature in August 2026.[1][9] On a two-qubit device, the roughly 500 ns gate flagged an erasure in about 0.5% of operations; with erasures discarded, randomized benchmarking gave 0.108% residual error per gate. A surface-code simulation with that error structure gave Λ, the factor by which logical error falls when code distance rises by two, of about 27, against about 14 for 0.1% depolarizing noise. The authors note that model counted only CZ errors and perfect erasure checks; adding single-qubit gate, measurement and idle errors lowers Λ.[9]<a href="https://oqc.tech/" target="_blank" rel="noopener noreferrer">Oxford Quantum Circuits</a>, also a dual-rail qubit developer, released Erado in March 2026: an open-source Qiskit-based library whose 16-qubit backend models erasure noise only and returns no per-shot erasure flags.[10][11][12][13] Quantum Circuits announced an error-aware simulator with real-time control flow for select customers in June 2024.[14] D-Wave's beta reports erasures per shot and mid-circuit, and models Pauli errors too. Its documented targets are 17 and 21 qubits; D-Wave's roadmap lists a 17-physical-qubit system for 2026.[4][8]The beta suits developers testing erasure-aware logic on one hardware model, not large circuits or calibrated fidelity estimates.<h2 id="isPasted">Technical Specifications</h2><h3>D-Wave gate-model simulator (Leap Beta, per Ocean SDK documentation, October 2026)</h3><h2 id="isPasted"> </h2><table><thead><tr><th>Spec</th><th>Value</th></tr></thead><tbody><tr><td>Emulated hardware</td><td>Dual-rail superconducting cavity qubits</td></tr><tr><td>Maximum circuit size</td><td>21 qubits</td></tr><tr><td>Simulator targets</td><td>DRsim_17qubits, DRsim_21qubits</td></tr><tr><td>Simulation method</td><td>Monte Carlo; runtime O(s·g·2ⁿ) for s shots, g gates, n qubits</td></tr><tr><td>Ideal mode</td><td>State vector, no noise; all Qiskit gates; mced() always returns 0</td></tr><tr><td>Noisy mode</td><td>Pauli errors, leakage and seepage applied randomly after gates and idles; basis gates only; same scaling, slower</td></tr><tr><td>Error injection</td><td>leak and seep instructions (noisy mode)</td></tr><tr><td>Basis gates (noisy mode)</td><td>sx, x, rz, cz</td></tr><tr><td>Measurement outcomes</td><td>0, 1, * (erased)</td></tr><tr><td>Mid-circuit error detection</td><td>mced(), non-destructive</td></tr><tr><td>Classical control</td><td>If, While, DoWhile, For</td></tr><tr><td>Post-selection</td><td>Repeat until the requested number of erasure-free shots is collected</td></tr><tr><td>Shots per job</td><td>1 to 1,000,000 (default 1,000)</td></tr><tr><td>Job time limit</td><td>1 to 2,700 s</td></tr><tr><td>Programming interfaces</td><td>QCDL (Python), Ocean SDK; Qiskit integration (D-Wave fact sheet)</td></tr><tr><td>Access</td><td>Leap cloud service, invited beta</td></tr><tr><td>Noise-model error rates</td><td>Not stated</td></tr><tr><td>Pricing</td><td>On request (Starter and Premium bundles announced June 2026)</td></tr><tr><td>General availability date</td><td>Not stated</td></tr></tbody></table><h3>Dual-rail CZ gate, two-qubit device (Nature, 5 August 2026)</h3><table><thead><tr><th>Spec</th><th>Value</th></tr></thead><tbody><tr><td>Gate duration</td><td>About 500 ns</td></tr><tr><td>Detected erasure per CZ gate</td><td>0.53% (repeated Bell-state tomography); 0.69% (interleaved randomized benchmarking)</td></tr><tr><td>Residual error per CZ gate, erasures discarded</td><td>0.108% (interleaved randomized benchmarking)</td></tr><tr><td>Single-qubit gates</td><td>About 0.1% erasure; about 0.01% residual error</td></tr><tr><td>Simulated surface-code Λ</td><td>About 27 (CZ errors only, perfect erasure checks); about 14 for 0.1% depolarizing noise</td></tr></tbody></table>Sources: [2][8][9][15][16]Everything in the first table describes a classical emulation whose runtime doubles with each added qubit. D-Wave's documentation and fact sheet do not give the error rates or qubit connectivity behind the noise model. That does not block prototyping control flow around erasure flags, but it does limit what noisy-mode results say about hardware fidelity. The gate figures come from a two-qubit device, and Aqumen Seeker, the dual-rail processor Quantum Circuits launched in November 2024, has 8 qubits. Neither is hardware at the 17- or 21-qubit scale the simulator emulates.[17]Recommended reading:<a href="https://www.wevolver.com/article/real-time-quantum-error-decoding-single-cpu-408-logical-qubits"> A Full Quantum Error Correction Stack for 408 Logical Qubits Ran on a Standard CPU</a>. IonQ's real-time decoder covers the classical side of acting on error information while a computation runs.<h2>References</h2><ol><li><a href="https://www.businesswire.com/news/home/20261001196673/en/D-Wave-Launches-Gate-Model-Simulator-Beta-Program-Advancing-Error-Aware-Programming-Capabilities">D-Wave Launches Gate-Model Simulator Beta Program, Advancing Error-Aware Programming Capabilities</a>, D-Wave Quantum via Business Wire, 1 October 2026</li><li><a href="https://www.hpcwire.com/off-the-wire/d-wave-to-launch-gate-model-quantum-simulator-with-dual-rail-error-detection/">D-Wave to Launch Gate-Model Quantum Simulator with Dual-Rail Error Detection</a>, HPCwire, 18 June 2026 (reprint of D-Wave's press release)</li><li><a href="https://www.dwavequantum.com/company/newsroom/press-release/d-wave-to-acquire-quantum-circuits">D-Wave Announces Agreement to Acquire Quantum Circuits Inc.</a>, D-Wave Quantum, 7 January 2026</li><li><a href="https://www.dwavequantum.com/company/newsroom/press-release/d-wave-reports-second-quarter-2026-results/">D-Wave Reports Second Quarter 2026 Results</a>, D-Wave Quantum, 6 August 2026 (includes the gate-model roadmap)</li><li><a href="https://rsl.yale.edu/sites/default/files/2023-teoh-et-al-2023-dual-rail-encoding-with-superconducting-cavities.pdf">Dual-rail encoding with superconducting cavities</a>, Teoh et al., PNAS, 2023 (peer-reviewed; Yale research that preceded the Quantum Circuits hardware)</li><li><a href="https://arxiv.org/pdf/2208.05461">Erasure qubits: Overcoming the T1 limit in superconducting circuits</a>, Kubica et al., arXiv, 2022 (AWS Center for Quantum Computing, Caltech and Hebrew University of Jerusalem)</li><li><a href="https://docs.dwavequantum.com/en/latest/ocean/api_ref_gate/index.html">dwave-gate</a>, D-Wave Ocean SDK documentation, version 0.6.0, accessed October 2026</li><li><a href="https://docs.dwavequantum.com/en/latest/ocean/api_ref_gate/workflow.html">Using dwave-gate</a>, D-Wave Ocean SDK documentation, version 0.6.0, accessed October 2026 (simulator modes, parameters and properties)</li><li><a href="https://www.nature.com/articles/s41586-026-10822-y">An entangling gate for dual-rail erasure qubits</a>, Mehta et al., Nature, 5 August 2026 (peer-reviewed, open access; authors at D-Wave and Yale)</li><li><a href="https://oqc.tech/company/newsroom/oqc-announces-dual-rail-dimon-research">OQC Announces Research on Path to Commercially-Viable Quantum Computers</a>, Oxford Quantum Circuits, 19 June 2025 (company press release)</li><li><a href="https://pypi.org/project/erado">erado</a>, Python Package Index, release history (version 1.0.0 released 11 March 2026)</li><li><a href="https://oqc.tech/resources/making-quantum-errors-visible">Making Quantum Errors Visible: A New Approach to Reliable Quantum Computing</a>, Oxford Quantum Circuits, 1 July 2026 (company blog)</li><li><a href="https://docs.oqc.app/qcaas-sdk/erado_simulator.html">Erado Basic Simulator</a>, OQC QCaaS SDK documentation, accessed October 2026</li><li><a href="https://thequantuminsider.com/2024/06/18/quantum-circuits-developing-quantum-software-platform-with-built-in-qubit-error-detection/">Quantum Circuits Developing Quantum Software Platform With Built-in Qubit Error Detection</a>, The Quantum Insider, 18 June 2024 (reprint of a Quantum Circuits press release)</li><li><a href="https://docs.dwavequantum.com/en/latest/ocean/api_ref_gate/qcdl.html">QCDL API reference</a>, D-Wave Ocean SDK documentation, version 0.6.0, accessed October 2026</li><li><a href="https://www.dwavequantum.com/media/40mpgr3t/gate-model-quantum-simulator.pdf">D-Wave's Gate-Model Quantum Simulator</a>, D-Wave product fact sheet, 2026</li><li><a href="https://quantumcircuits.com/resources/quantum-circuits-accelerates-momentum/">Quantum Circuits Accelerates Momentum Toward Commercial Quantum Computing With New Aqumen Seeker Quantum Processing Unit</a>, Quantum Circuits, 19 November 2024 (company press release)</li></ol>

D-Wave, supplier of quantum computers, has opened a limited cloud beta of a 21-qubit emulator for gate-model hardware it has yet to release.

Dual-rail qubit emulator lets quantum programs act on detected errors

In this episode, we speak with Michael Corr, co-founder and CEO of Duro, and Justin Sears, head of product marketing at Altium, about how connected cloud platforms are changing hardware development.

Michael Corr & Justin Sears on How Altium & Duro Fuel the Next Generation of Hardware Startups

If you see a doctor regularly, chances are you have had a lipid panel ordered and your blood drawn at a lab. The results told your physician about your levels of cholesterol and triglycerides, factors that play a role in diagnosing conditions such as cardiovascular diseases and diabetes. Now, a team led by Wei Gao, a professor in Caltech's Cherng Department of Medical Engineering, has developed a stick-on patch capable of gathering the same lipid measurements by analyzing sweat. And it can do so not just once but continuously.The new noninvasive sensor uses machine learning to estimate levels of lipids in the blood based on what is measured in the sweat. The relationship between lipids in sweat and lipids in blood is not linear—a plot of the relationship between measurements and what is found in the blood does not follow a straight line. The causal machine learning model takes into consideration various physiological factors that might affect those sweat measurements such as body mass index (BMI), sex, and how much a person is sweating to produce an estimate of blood lipid levels.<img src="https://s3-us-west-1.amazonaws.com/wevolver-project-images/froala%2F1790844786498-heading+%288%29.jpg" style="width:100%px" class="fr-fic fr-dib" />The new, inexpensive stick-on sweat sensor measures lipid levels, offering a noninvasive way to continuously monitor cholesterol and triglycerides."Together, the sweat measurement and the causal machine learning model can predict the blood level with high accuracy," says Gao, who is also a Heritage Medical Research Institute Investigator.Gao and his colleagues describe the new lipid profiling device and results of preclinical testing on 24 participants in a paper in the journal Nature Sensors. The lead authors of the paper are all from Gao's group at Caltech: José A. Lasalde-Ramírez, a graduate student; Chihyeong Won, a visitor at Caltech; and Sijie Ji, a senior postdoctoral scholar research associate.Gao says the wearable device could play an important role in giving people an early warning related to cardiovascular or metabolic diseases. "How many people actually get their blood drawn regularly? I haven't done this myself for at least two years probably," Gao says. "That's why we think a noninvasive way of monitoring lipids will be critical."Gao's group has previously developed noninvasive tests for <a href="https://www.caltech.edu/about/news/science-sweat-interview-wei-gao-79854">glucose</a> and <a href="https://www.caltech.edu/about/news/wearable-sweat-sensor-detects-gout-causing-compounds">uric acid</a>, but he says the continuous detection of lipids posed a bigger challenge. For example, much of the cholesterol in sweat is present in a chemical form called esterified cholesterol, which cannot be detected directly. The researchers therefore developed a two-step enzymatic reaction: The first step converts esterified cholesterol into free cholesterol, and the second oxidizes the free cholesterol to generate hydrogen peroxide, which can then be measured by the sensor. They also had to figure out a way to trap a supply of ATP (adenosine triphosphate), the cell's primary energy source, in a special polymer built into the wearable patch. That way it could gradually release ATP into a user's sweat, allowing the polymer system to sustain the ATP supply needed for triglyceride sensing for more than 20 hours.The paper is titled "Non-invasive continuous lipid profiling via cofactor-refreshing cascading enzymatic reactions and causal machine learning." Authors Soyoung Shin, Robin M. McDonald, Katherine Karish, Gwangmook Kim, Hong Hang, Daniel Mukasa, Yu Song, and Juliane R. Sempionatto, contributed to the work while at Caltech. Sempionatto also contributed while at Rice University. Brian Arianpour, Tzung K. Hsiai, and Zhaoping Li are authors from UCLA. Li and author Jieping Yang are from the David Geffen School of Medicine at UCLA. The work was supported by funding from the National Science Foundation, the National Institutes of Health, Samsung Research America, and the Heritage Medical Research Institute.

The new noninvasive sensor uses machine learning to estimate levels of lipids in the blood based on what is measured in the sweat.

Sweat Sensor Enables Continuous Noninvasive Measurement of Cholesterol

<h2 id="isPasted">September 28th 2026 Efinix announced the Sapphire RV64 soft SoC</h2>The Sapphire RV64's CPU cores, caches and peripherals are built from FPGA logic, with DRAM reached through the FPGA's hardened DDR interface. It uses one to four cores derived from VexiiRiscv, an MIT-licensed open-source RISC-V CPU. Each core has a seven-stage in-order pipeline implementing RV64IM with optional A, F, D, C, Zba, Zbb, Zbs and Zicbom extensions; Efinix lists Linux support via an optional Sv39 MMU.[1][2][3]Efinix aims it at designs that have "outgrown the performance, addressable memory, cache, and I/O limits of 32-bit embedded cores". Support covers all Efinix's Titanium and Topaz FPGAs (its 16 nm families) and Trion devices (its first-generation 40 nm family) from the T20 up.[1][4][5]<h2>Why it matters</h2>The step from the company's 32-bit Sapphire SoC is mostly about memory. The 32-bit version addresses up to 3.5 GB of DRAM and has L1 caches only. Sapphire RV64 addresses up to 8 GB of DDR3 or LPDDR4x and adds a shared 64 to 512 KB L2 cache.[2][6] With the L2 enabled, it also keeps two AXI DMA ports from user logic coherent, so accelerators in the fabric share cached memory without software flushes.[2]The 32-bit Sapphire already runs Linux; Efinix's br2-efinix Buildroot tree now builds Linux 6.6 for Sapphire RV64 too, so far only for the Titanium Ti375 C529 development board.[7][8] The gain is address reach: Sv39 gives software a 512 GB virtual address space, and the physical map places 8 GB of DRAM and a 64 GB cached AXI window above the 4 GB a 32-bit address spans.[2]Raw speed is modest. On the Ti375 board one Sapphire RV64 core scores 1.23 to 1.57 CoreMark/MHz, and fMAX is 250 to 278 MHz on the Ti375 and 65 to 77 MHz on a Trion T120. On that T120, the nearest published 32-bit Sapphire configuration reaches 115 MHz in 7,391 logic/adders, against 77 MHz and 10,741 for the most basic 64-bit build.[2][9] The Ti375 also carries a hardened quad-core 32-bit RISC-V block, which Efinix benchmarks at 2.345 CoreMark/MHz at 1 GHz.[10][11][12] Multiplying score by clock (our calculation, if per-MHz scores hold across clocks and compilers), the best soft configuration gives about 400 CoreMark per core, a hard core about 2,300.Where a hard CPU exists, Sapphire RV64's case rests on memory reach: up to 8 GB of DRAM against the hard block's 3.7 GB, and two cache-coherent DMA ports against its one AXI slave. It fits best on Trion, on Titanium and Topaz parts without the hardened block, and in 32-bit Sapphire designs that need more memory.[2][12][13]AMD's MicroBlaze V soft core already offers a 64-bit Sv39 implementation, with a Linux preset listed at 199 to 258 MHz on UltraScale+ devices; Lattice's RISC-V RX is 32-bit.[14][15][16]<h2>Technical specifications</h2><h3>Sapphire RV64 SoC: configurable range</h3><div><table><thead><tr><th>Spec</th><th>Value</th></tr></thead><tbody><tr><td>CPU</td><td>1 to 4 VexiiRiscv cores, 7-stage in-order pipeline, little-endian; machine and supervisor modes</td></tr><tr><td>ISA</td><td>RV64IM; optional A, F, D, C, Zba, Zbb, Zbs, Zicbom</td></tr><tr><td>System clock setting</td><td>20 to 400 MHz (achieved clock limited by device fMAX)</td></tr><tr><td>L1 cache</td><td>Instruction and data, 1, 2, 4 or 8 ways of 4 KB each; write-back data cache</td></tr><tr><td>L2 cache</td><td>Optional, shared, 64, 128, 256 or 512 KB, 8-way; coherency point for DMA</td></tr><tr><td>On-chip RAM</td><td>4 to 512 KB, with SPI flash boot loader</td></tr><tr><td>External memory</td><td>DDR3 at 800 Mbps, LPDDR4x at 3,200 Mbps, HyperRAM at 500 Mbps; 4 MB to 8 GB; DDR requires the FPGA's hardened DDR controller (Trion's supports DDR3, LPDDR3 and LPDDR2)</td></tr><tr><td>Memory bus</td><td>AXI4 full-duplex or AXI3 half-duplex, 32 to 512 bits</td></tr><tr><td>User-logic ports</td><td>Up to 2 coherent AXI4 slave (DMA) ports, 32 to 512 bits; up to 2 AXI4 master ports: A (AXI-Lite compatible, 256 MB uncached I/O region) and B (burst-capable, 64 GB cached region)</td></tr><tr><td>Memory management</td><td>Optional Sv39 MMU; optional PMP at 4 KB granularity</td></tr><tr><td>Interrupt handling</td><td>PLIC and CLINT; direct-mode trap vectors only (no vectored mode)</td></tr><tr><td>Other options</td><td>FPU (single or single plus double precision); BTB, RAS and gshare branch predictor; hardware and software prefetchers; custom-instruction interface with 1,024 IDs</td></tr><tr><td>Peripherals</td><td>Up to 32 GPIO, 5 I2C, 3 SPI, 3 UART, 3 timers, 8 user interrupts, 5 APB3 slave ports; watchdog</td></tr><tr><td>Debug</td><td>RISC-V debug specification through the FPGA's JTAG User TAP, up to 4 hardware breakpoints, co-debug with the FPGA debugger; no GPIO-based soft debug TAP</td></tr><tr><td>Linux support</td><td>br2-efinix Buildroot tree: Linux 6.6, U-Boot 2025.01, OpenSBI 1.6; RV64 build for the Titanium Ti375 C529 development board</td></tr><tr><td>Supported FPGAs</td><td>All Titanium and Topaz; Trion T20 and above</td></tr><tr><td>License terms and price</td><td>Not stated</td></tr></tbody></table></div><h3>Sapphire RV64 single-core benchmark configurations (Efinix's Efinity design software, version 2026.1)</h3><div><table><thead><tr><th>Spec</th><th>Basic L1</th><th>Basic L2</th><th>Advanced L1</th><th>Advanced L2</th></tr></thead><tbody><tr><td>CoreMark/MHz (Ti375 board)</td><td>1.23</td><td>1.25</td><td>1.56</td><td>1.57</td></tr><tr><td>Dhrystone/MHz (Ti375 board)</td><td>1.17</td><td>1.17</td><td>1.37</td><td>1.54</td></tr><tr><td>fMAX, Titanium Ti375 C529</td><td>271 MHz</td><td>278 MHz</td><td>250 MHz</td><td>252 MHz</td></tr><tr><td>fMAX, Topaz Tz170 J484</td><td>176 MHz</td><td>170 MHz</td><td>164 MHz</td><td>167 MHz</td></tr><tr><td>fMAX, Trion T120 F324</td><td>77 MHz</td><td>77 MHz</td><td>65 MHz</td><td>65 MHz</td></tr><tr><td>Logic/adders, Ti375</td><td>10,740</td><td>14,258</td><td>23,838</td><td>27,250</td></tr><tr><td>Memory blocks, Ti375</td><td>91</td><td>188</td><td>128</td><td>225</td></tr><tr><td>DSP48 blocks, all three devices</td><td>17</td><td>17</td><td>17</td><td>17</td></tr></tbody></table></div>Sources: [1][2][5][8][17]All four configurations use 1-way 4 KB L1 caches and a 256-bit AXI4 memory bus; the L2 variants add 64 KB of L2. Basic enables the I, M, A and C extensions; Advanced enables every extension except Zicbom plus all optional features.[2] All published figures are single-core. Advanced roughly doubles logic for about a quarter more CoreMark/MHz, and at each configuration's Ti375 fMAX the gain narrows to about 14% (our calculation: 27,250 against 14,258 logic/adders; 252 × 1.57 against 278 × 1.25). Efinix notes that enabling custom instructions, the FPU or the Linux MMU affects fMAX.[17]<h2> </h2>Recommended Reading:<a href="https://www.wevolver.com/article/risc-v-architecture"> RISC-V Architecture: A Comprehensive Guide to the Open-Source ISA</a>. Background on the RV32 and RV64 base ISAs, the standard extensions and the privilege modes that an Sv39 MMU relies on.<h2>References</h2><ol><li><a href="https://www.efinixinc.com/company-pr-efinix-brings-64-bit-riscv-performance-to-embeddded-fpga-designs-with-new-sapphire-rv64-soc.html">Efinix Brings 64-Bit RISC-V Performance to Embedded FPGA Designs With New Sapphire RV64 SoC</a>, Efinix, 28 September 2026. Company press release.</li><li><a href="https://www.efinixinc.com/docs/riscv-sapphire-rv64-ds-v1.0.pdf">Sapphire RV64 SoC Data Sheet, DS-SAPPHIRE-RV64 v1.0</a>, Efinix, May 2026.</li><li><a href="https://github.com/SpinalHDL/VexiiRiscv">VexiiRiscv</a>, SpinalHDL, accessed 30 September 2026. Open-source project repository.</li><li><a href="https://www.businesswire.com/news/home/20240711244170/en/Efinix-Releases-Topaz-Line-of-FPGAs-Delivering-High-Performance-and-Low-Power-to-Mass-Market-Applications">Efinix Releases Topaz Line of FPGAs, Delivering High Performance and Low Power to Mass Market Applications</a>, Business Wire, 11 July 2024. Company press release.</li><li><a href="https://www.efinixinc.com/docs/trion-overview-v3.3.pdf">Trion FPGA Overview v3.3</a>, Efinix, 2025.</li><li><a href="https://www.efinixinc.com/docs-html/rv32-sapphire-ds/topics/riscv-saxon-efx-features-sapphire.html">Sapphire RV32 SoC Data Sheet: Features</a>, Efinix, accessed 1 October 2026.</li><li><a href="https://efinixinc.com/products-linux-riscv.html">Linux + RISC-V Sapphire SoC</a>, Efinix, accessed 1 October 2026.</li><li><a href="https://github.com/Efinix-Inc/br2-efinix">BR2-Efinix: Buildroot external tree for building Linux for Efinix RISC-V Sapphire SoC</a>, Efinix, branch 2025.02, accessed 1 October 2026. Company board support package.</li><li><a href="https://www.efinixinc.com/support/ip/riscv-sapphire.php">Sapphire RISC-V SoC</a>, Efinix, accessed 1 October 2026. Product page for the 32-bit soft SoC, with resource and fMAX tables.</li><li><a href="https://www.businesswire.com/news/home/20240401675642/en/Efinix%E2%80%99s-Titanium-Ti375-Sampling-Unlocking-and-Delivering-Mainstream-Edge-Intelligence-Innovation">Efinix's Titanium Ti375 Sampling; Unlocking and Delivering Mainstream Edge Intelligence Innovation</a>, Business Wire, 1 April 2024. Company press release.</li><li><a href="https://www.efinixinc.com/docs-html/riscv-sapphire-hpb-ug/topics/riscv-performance-hpb.html">High-Performance Sapphire SoC User Guide: Performance</a>, Efinix, accessed 30 September 2026. Vendor benchmark results.</li><li><a href="https://www.efinixinc.com/docs-html/rv32-sapphire-hpb-ds/topics/riscv-saxon-efx-features-sapphire-hpb.html">High-Performance Sapphire RV32 SoC Data Sheet: Features</a>, Efinix, accessed 1 October 2026.</li><li><a href="https://www.efinixinc.com/support/ip/riscv-sapphire-hpb.php">High-Performance Sapphire RV32 SoC</a>, Efinix, accessed 1 October 2026. Product page for the hardened block.</li><li><a href="https://docs.amd.com/r/en-US/ug1629-microblaze-v-user-guide/Resource-Utilization">MicroBlaze V Processor Reference Guide (UG1629): Resource Utilization</a>, AMD, release 2026.1, 31 July 2026.</li><li><a href="https://docs.amd.com/r/en-US/ug1629-microblaze-v-user-guide/Memory-Architecture">MicroBlaze V Processor Reference Guide (UG1629): Memory Architecture</a>, AMD, release 2026.1, 31 July 2026.</li><li><a href="https://www.latticesemi.com/Products/DesignSoftwareAndIP/IntellectualProperty/IPCore/IPCores04/RISC-V-RX-CPU">RISC-V RX CPU IP Core</a>, Lattice Semiconductor, accessed 30 September 2026.</li><li><a href="https://www.efinixinc.com/docs/riscv-sapphire-rv64-ug-v1.0.pdf">Sapphire RV64 SoC User Guide, UG-SAPPHIRE-RV64 v1.0</a>, Efinix, May 2026.</li></ol>

Up to four 64-bit RISC-V cores, a coherent L2 cache and a Linux-capable Sv39 MMU built from FPGA logic.

New 64-bit RISC-V soft SoC for FPGAs with 8 GB DRAM reach

<h2>Key Takeaways</h2><ul><li>The surface finish chart below converts between Ra in micrometers, Ra in microinches, and ISO N-grades.</li><li>For most machined surfaces, Rq (RMS) is about 11% higher than the Ra value, but you cannot obtain an accurate Rq from Ra alone.</li><li>N-grades come from ISO 1302, which ISO records as withdrawn and replaced by ISO 21920-1:2021. But they still appear on drawings, so you still need to read them.</li></ul><h2>The Surface Finish Chart</h2>This is the core conversion table, with the first three columns taken directly from ISO 1302.[1] Ra is the reference column, because every other unit here is derived from it or maps onto it.<div><table><tbody><tr><td>N-grade</td><td>Ra (µm)</td><td>Ra (µin)</td><td>Typical Rq/RMS (µin)</td><td>Notes</td></tr><tr><td>N1</td><td>0.025</td><td>1</td><td>1.1</td><td> </td></tr><tr><td>N2</td><td>0.05</td><td>2</td><td>2.2</td><td> </td></tr><tr><td>N3</td><td>0.1</td><td>4</td><td>4.4</td><td> </td></tr><tr><td>N4</td><td>0.2</td><td>8</td><td>8.9</td><td> </td></tr><tr><td>N5</td><td>0.4</td><td>16</td><td>17.8</td><td>Finest as-machined finish[2]</td></tr><tr><td>N6</td><td>0.8</td><td>32</td><td>35.5</td><td> </td></tr><tr><td>N7</td><td>1.6</td><td>63</td><td>69.9</td><td> </td></tr><tr><td>N8</td><td>3.2</td><td>125</td><td>138.8</td><td>Standard as-machined finish[2]</td></tr><tr><td>N9</td><td>6.3</td><td>250</td><td>277.5</td><td> </td></tr><tr><td>N10</td><td>12.5</td><td>500</td><td>555</td><td> </td></tr><tr><td>N11</td><td>25.0</td><td>1000</td><td>1110</td><td> </td></tr><tr><td>N12</td><td>50.0</td><td>2000</td><td>2220</td><td> </td></tr></tbody></table></div>The Rq column is computed as Ra × 1.11 for reasons explained below.Note that the microinch and micrometer columns are the conventional rounded pairs, not exact conversions.<h2>How to Read This Surface Finish Chart</h2>Ra, Rq, Rz, and Rt are all roughness parameters computed from the same measured roughness profile, so one measurement can report several of them at once.<h3>Ra</h3>Ra is the arithmetic mean of the absolute height deviations of the roughness profile from the mean line, measured over the evaluation length.[3] ASME B46.1-2019 gives the discrete form used by digital instruments as:[3]Ra = (|Z1| + |Z2| + |Z3| ... |ZN|) / NWhere each Z value is a measurement of an absolute deviation (either a peak or a valley) from the mean line. N represents the total number of measurements taken.The abbreviations on older drawings all mean the same measurement:<div><table><tbody><tr><td>Abbreviation</td><td>Stands for</td><td>Notes</td></tr><tr><td>Ra</td><td>Roughness average</td><td>Current ISO and ASME designation</td></tr><tr><td>CLA</td><td>Center line average</td><td>Older British usage. Numerically identical to Ra in µin</td></tr><tr><td>AA</td><td>Arithmetic average</td><td>Older American usage. Same measurement</td></tr><tr><td>Rq</td><td>Quadratic mean</td><td>A different calculation, not a different name. See below</td></tr><tr><td>RMS</td><td>Root mean square</td><td>The same as Rq</td></tr></tbody></table></div><h3>Rq</h3>Rq, sometimes written as RMS, is the square root of the mean of the squared height deviations. Squaring before averaging weights large peaks and valleys more heavily than Ra does, so Rq always reads slightly higher than Ra on the same surface profile.[4]For most machined surfaces, Rq is approximately 11% higher than Ra, giving the rule of thumb Rq ≈ Ra × 1.11.[5] That factor is exact only for an idealized sinusoidal profile—a surface that rises and falls with perfectly consistent repetition. Real surfaces depart from it, and the rougher and less regular the surface, the less reliable it becomes. In other words, you cannot get an exact Rq value from your Ra value; you need data from the measured profile to calculate it.<h3>N-grades</h3>N-grades, defined by ISO 1302, compress a roughness specification into a single number from N1 to N12, and each step roughly doubles Ra.[1]However, ISO 1302:2002 has been withdrawn and replaced by ISO 21920-1:2021.[1][6]So N-grades are a notation from a superseded standard. They have not vanished from drawings, which is why the chart includes them, but a new drawing is better served by an explicit Ra value with its cutoff stated. If you are updating drawing templates, note that ISO 21920-1 also changed the default acceptance rule to the maximum rule.[6]<h3>Rz</h3>Ra and Rz describe different things. Ra averages every deviation from the mean line, while Rz averages the most extreme deviations from each sampling length, so it is more sensitive to pronounced peaks and valleys.[4] Two surfaces with the same Ra value can have very different Rz values depending on whether the roughness profile is uniform or punctuated by isolated scratches and burrs. One value cannot be converted from the other.Recommended reading: <a href="https://www.wevolver.com/article/ra-vs-rz-understanding-surface-roughness-parameters-in-engineering" target="_blank" rel="noopener noreferrer">RA vs RZ: Understanding Surface Roughness Parameters in Engineering</a><h3>Cutoff λc</h3>A surface roughness value is incomplete without its filter cutoff, and this is the single most common reason two parties measuring the same part disagree.The cutoff separates roughness from waviness. ASME B46.1-2019 demonstrates the effect on one measured profile: at a 0.8 mm cutoff it reports Ra 0.057 µm, at 0.25 mm it reports 0.044 µm, and at 0.08 mm it reports 0.028 µm.[3]When the drawing does not state a cutoff, B46.1-2019 gives guideline values selected from the measured Ra.[3]<div><table><tbody><tr><td>Ra (µm)</td><td>Cutoff λc (mm)</td><td>Evaluation length L (mm)</td></tr><tr><td>up to 0.02</td><td>0.08</td><td>0.40</td></tr><tr><td>0.02 to 0.10</td><td>0.25</td><td>1.25</td></tr><tr><td>0.10 to 2.0</td><td>0.80</td><td>4.0</td></tr><tr><td>2.0 to 10.0</td><td>2.5</td><td>12.5</td></tr><tr><td>over 10.0</td><td>8.0</td><td>40.0</td></tr></tbody></table></div>Most machined work falls in the 0.10 to 2.0 µm band, which is why a 0.8 mm cutoff and a 4.0 mm evaluation length is the common default. The sampling length equals the cutoff when a filter is used.[3]<h3>Lay</h3>Lay, the predominant direction of the surface pattern, is specified separately from the roughness number.[3] It is called out with its own symbol set, including R for radial and C for circular. Surface finish symbols indicate lay, the parameter, the limit, and the cutoff together on the drawing.Recommended reading: <a href="https://www.wevolver.com/article/surface-finish-standards" target="_blank" rel="noopener noreferrer">Surface Finish: Parameters, Standards, and How to Specify It</a><h2>Ra Values by Manufacturing Process</h2><img src="https://images.wevolver.com/eyJidWNrZXQiOiJ3ZXZvbHZlci1wcm9qZWN0LWltYWdlcyIsImtleSI6ImZyb2FsYS8xNzkwODIwNzIxODI3LXNodXR0ZXJzdG9ja18xOTcyNjAxNTM3LmpwZyIsImVkaXRzIjp7InJlc2l6ZSI6eyJ3aWR0aCI6OTUwLCJmaXQiOiJjb3ZlciJ9fX0=" style="width:100%px" class="fr-fic fr-dib" />Grinding can produce a fine surface finishDifferent processes can achieve different levels of surface smoothness. However, which exact finish a manufacturing process can reach depends on the material, the tooling, the machine, and the parameters.<div><table><tbody><tr><td>Process</td><td>Typical Ra (µm)</td><td>Quality band</td></tr><tr><td>Lapping</td><td>0.1 to 0.2[7]</td><td>Very fine</td></tr><tr><td>Honing</td><td>0.2 to 0.4[7]</td><td>Fine</td></tr><tr><td>Grinding</td><td>0.4[7]</td><td>Fine</td></tr><tr><td>CNC turning</td><td>3.2[2]</td><td>Medium to fine</td></tr><tr><td>CNC milling</td><td>3.2[2]</td><td>Medium</td></tr><tr><td>Rough machining</td><td>25[5]</td><td>Rough</td></tr><tr><td>Sand casting</td><td>50[5]</td><td>Rough</td></tr></tbody></table></div>Within any one process, the finish is driven by the details. In <a href="https://www.wevolver.com/tag/cnc-machining" target="_blank" rel="noopener noreferrer">CNC machining</a>, feed rate, spindle rpm, tool nose radius, rigidity and tool wear all affect the achievable finish, which is why the same nominal operation on two machines will not give you the same surface texture.Secondary operations are equally important. Honing refines a bore beyond what boring alone reaches, deburring removes the burrs left at cut edges, and bead blasting produces a uniform matte non-directional texture. Powder coating and similar coatings add a layer that inherits and modifies the texture underneath.Bulk-forming processes sit at the coarse end, and the surface roughness values of processes like forging and rolling are usually a starting condition to be machined away rather than a finish to be met.<h2 id="isPasted">The Price of Lower Ra Values</h2>Surface finish generally becomes more expensive as the required Ra decreases. Rough machining can achieve relatively high Ra values with standard cutting tools and short cycle times, while finer finishes require slower feeds, sharper or more specialized tooling, and better machine stability.[5] Once conventional machining approaches its practical limit, processes such as grinding, honing, lapping, polishing, or superfinishing may be needed, adding both processing time and setup costs.[7]The relationship is not linear. Reducing Ra from 3.2 to 1.6 µm may require only a modest change in machining conditions, while reducing it from 0.8 to 0.4 µm can require a substantially different process. For this reason, specifying a finer surface finish than the function of the part requires can increase manufacturing cost without providing a corresponding benefit.<h2>Abrasive Grit to Ra</h2>Abrasive grit numbers map onto Ra only loosely, and the mapping depends on which grit scale is being quoted. The bands below are on the FEPA P-scale for coated abrasives, standardized as ISO 6344.[6]<div><table><tbody><tr><td>Grit (FEPA P)</td><td>Ra (µm), approx.</td><td>Ra (µin), approx.</td><td>Typical use</td></tr><tr><td>P40 to P60</td><td>3 to 5</td><td>120 to 200</td><td>Stock removal, weld knock-down</td></tr><tr><td>P80 to P120</td><td>1.5 to 3</td><td>60 to 120</td><td>Blending, coarse shaping</td></tr><tr><td>P150 to P240</td><td>0.8 to 1.5</td><td>32 to 60</td><td>Pre-finish smoothing</td></tr><tr><td>P320 to P600</td><td>0.3 to 0.8</td><td>12 to 32</td><td>Finishing, sealer scuff</td></tr><tr><td>P800 to P1200</td><td>0.1 to 0.3</td><td>4 to 12</td><td>Polish preparation</td></tr><tr><td>P1500 and finer</td><td>under 0.1</td><td>under 4</td><td>Pre-buff, high-gloss start</td></tr></tbody></table></div><h2>How the Measurement Is Taken</h2><img src="https://images.wevolver.com/eyJidWNrZXQiOiJ3ZXZvbHZlci1wcm9qZWN0LWltYWdlcyIsImtleSI6ImZyb2FsYS8xNzkwODIwNzY1NzA5LXNodXR0ZXJzdG9ja18xMzcyNjQ3NjI5LmpwZyIsImVkaXRzIjp7InJlc2l6ZSI6eyJ3aWR0aCI6OTUwLCJmaXQiOiJjb3ZlciJ9fX0=" style="width:100%px" class="fr-fic fr-dib" alt="A contact surface roughness tester" />A contact roughness tester or profilometerSurface finish measurement varies depending on the equipment used.A contact surface roughness tester drags a stylus of known tip radius across the surface at fixed speed and records height data at a set interval.[3] These instruments, generally called profilometers, produce the surface profile that every parameter in the chart is computed from.A non-contact method uses optical interaction instead: focus variation, confocal microscopy or interferometry. Optical instruments capture an area rather than a single line, which matters when the texture of a surface is directional.<h2>Conclusion</h2>A surface finish chart is a unit converter, but it cannot tell you what Rz corresponds to your Ra, because that depends on the shape of the roughness profile. Use the chart to translate between units, then specify the parameter, the limit, the cutoff, and the standard explicitly on your technical drawings. Then the number will mean the same thing to you and to whoever makes the part.<h2>Frequently Asked Questions</h2>What does a 32 surface finish mean?Ra 32 µin, equivalently Ra 0.8 µm or N6, a general engineering finish.What is the difference between Ra and Rq?Ra averages the absolute deviations from the mean line; Rq squares them first, which weights large peaks and valleys more heavily. On the same profile Rq typically reads about 11% higher, so RMS ≈ Ra × 1.11 as a rule of thumb.[5] They are two calculations on one measurement, not two measurements.Is CLA the same as Ra?Yes. Center line average is an older name for the same arithmetic average measurement.How do I convert Ra to Rz?You cannot do it reliably, as the Ra value has already “smoothed out” the extremes of which Rz is a measure.Are N-grades still valid?They come from ISO 1302, which ISO lists as withdrawn and replaced by ISO 21920-1:2021.[1][6] They remain common on existing drawings, so you still need to read them, but new drawings are better served by an explicit Ra value with its cutoff.Why do two shops measure the same part differently?Usually the filter cutoff. ASME’s own example gets Ra 0.057 µm and Ra 0.028 µm from one profile by changing the cutoff.[3]What Ra can CNC machining reach?Roughly 3.2 µm as machined, down to about 0.4 µm with further finishing passes.[2]<h2>References</h2>[1] International Organization for Standardization. <a href="https://www.iso.org/standard/28089.html" target="_blank">ISO 1302:2002: Geometrical Product Specifications (GPS) — Indication of surface texture in technical product documentation</a>. Geneva: ISO; 2002.[2] Protolabs Network. <a href="https://www.hubs.com/knowledge-base/surface-finishes-cnc-machinings/#surface-finishes-explained-as-machined" target="_blank">What are the types of surface finishes for CNC machining?</a> [Internet]. Protolabs Network; [cited 2026 Sep 30].[3] American Society of Mechanical Engineers. <a href="https://www.asme.org/getmedia/f22128e5-acad-429d-bc75-0ac4bdffdf44/b46-1-2019-11x17-poster.pdf" target="_blank">B46.1-2019: Surface texture (surface roughness, waviness, and lay): reference poster</a>. New York: ASME; 2019.[4] Keyence. <a href="https://www.keyence.com/products/microscope/laser-microscope/resources/laser-microscope-resources/how-surface-height-is-quantified-from-ra-to-rz.jsp" target="_blank">How surface height is quantified, from Ra to Rz</a> [Internet]. Keyence; [cited 2026 Sep 30].[5] Astro Pak. <a href="https://astropak.com/surface-roughness-average-ra/" target="_blank">Surface roughness average (Ra): chart, formula, and conversion calculator</a> [Internet]. Astro Pak; [cited 2026 Sep 30].[6] International Organization for Standardization. <a href="https://www.iso.org/obp/ui/#iso:std:iso:21920:-1:ed-1:v1:en" target="_blank">ISO 21920-1:2021: Geometrical Product Specifications (GPS) — Surface texture: Profile — Part 1: Indication of surface texture</a>. Geneva: ISO; 2021.[7] Grzesik W, Kruszynski B, Ruszaj A. <a href="https://link.springer.com/chapter/10.1007/978-1-84882-874-2_5" target="_blank">Surface integrity of machined surfaces</a>. In: Grzesik W, editor. Surface integrity in machining. London: Springer London; 2010. p. 143-179.[8] Whitby Abrasives. <a href="https://whitbyabrasives.ca/blogs/news/grit-to-surface-finish-ra-chart" target="_blank">Grit-to-surface-finish (Ra) chart</a> [Internet]. Whitby Abrasives; [cited 2026 Sep 30].

Surface finish can be specified in many different ways

A reference chart for converting between surface finish units, plus Ra values by manufacturing process and the relationship between surface

Surface Finish Chart: Ra, Rq, and N-Grade Conversions

<h2 id="isPasted">Lattice Semiconductor announced the Mach-N2 Family:</h2>The Mach-N2 is the newest generation of Lattice's secure-control FPGAs, which handle power sequencing, system management and security. Mach-N2 shares Nexus 2, Lattice's 16 nm FinFET platform, with the general-purpose Certus-N2 family, adding internal flash and run-time security. Its five devices span 40k to 135k LUTs, or 65k to 220k system logic cells.[1][2][3]Lattice says Mach-N2 pairs a hardware root of trust with crypto-agile post-quantum cryptography (PQC) compliant with CNSA 2.0, the NSA's algorithm suite for national security systems. It also claims up to twice the logic density for system control functions and sub-30 ms boot for the 220k-cell device.[1] Hardware PQC sits on one device, the 215k-cell MH21D.[2]<h2>Why it matters</h2>Lattice pitches Mach-N2 as a first-on, last-off device.[4] In NIST's platform firmware resiliency model, SP 800-193, a root of trust protects firmware, detects corruption and restores a known-good image.[5] The NSA prioritises firmware signing, whose algorithms are "frequently locked in for the life of a system". CNSA 2.0 lists hash-based LMS and XMSS for firmware signing, ML-DSA-87 for signatures and ML-KEM-1024 for key establishment, and new national security system acquisitions must comply from January 1, 2027.[6]The MH21D adds ML-DSA, LMS, XMSS and stateless hash-based SLH-DSA signatures, plus ML-KEM key exchange, to the classical cryptography all five devices share.[2] Lattice's previous PQC-capable parts belong to its MachXO5-NX secure-control family, whose TDQ devices launched in October 2025 on 28 nm FD-SOI and now reach 64k logic cells with PCIe Gen2 x1.[7][8] The MH21D's 132k LUTs are about 2.5 times the largest TDQ device's roughly 53k (author's calculation, 64k cells ÷ 1.2 cells per LUT), and its hard PCIe controller runs Gen4 x4.[2]The MH21D comes only in an 18 × 18 mm CBG484 package with 236 user I/O and in the two slower speed grades; it needs customer keys and policy provisioned before first use. Mach-N2 tops out at 248 user I/O, 92 of them 3.3 V-capable, where the largest MachXO5-NX packages reach 360 or more, over 300 of them 3.3 V-capable. Mach-N2 also drops the 12-bit SAR ADCs that MachXO5-NX provides for system monitoring.[2][8][9]Some competing FPGAs already offer post-quantum boot. AMD's cost-optimised Spartan UltraScale+ SU200P targets board management and platform root of trust with up to 572 I/O and up to eight transceivers. The SU200P authenticates boot images with hash-based HSS/LMS signatures or ECDSA P-384 and receives its configuration from external memory or a host at every power-up.[10][11][12] Altera said in September that PQC-enabled Agilex 3 and Agilex 5 FPGAs are shipping.[13] Mach-N2 instead boots from internal flash; Lattice says configuration data is never exposed outside the device while loading.[14]<h2>Technical specifications</h2><h3>Mach-N2 devices</h3><div><table><thead><tr><th>Spec</th><th>MH06</th><th>MH10</th><th>MH16</th><th>MH20</th><th>MH21D</th></tr></thead><tbody><tr><td>System logic cells</td><td>65k</td><td>100k</td><td>160k</td><td>220k</td><td>215k</td></tr><tr><td>LUTs</td><td>40k</td><td>61k</td><td>98k</td><td>135k</td><td>132k</td></tr><tr><td>Block RAM (36 kbit blocks)</td><td>114</td><td>153</td><td>228</td><td>306</td><td>289</td></tr><tr><td>18 × 18 multipliers</td><td>120</td><td>240</td><td>360</td><td>520</td><td>520</td></tr><tr><td>Hardware PQC and crypto agility</td><td>No</td><td>No</td><td>No</td><td>No</td><td>Yes</td></tr><tr><td>Packages (0.8 mm pitch)</td><td>CBG256 (14 × 14 mm), CBG484 (18 × 18 mm)</td><td>CBG256, CBG484</td><td>CBG484</td><td>CBG484</td><td>CBG484</td></tr><tr><td>User I/O, total (3.3 V-capable wide-range / high-performance)</td><td>141 (39 / 102) in CBG256; 196 (92 / 104) in CBG484</td><td>141 (39 / 102) in CBG256; 196 (92 / 104) in CBG484</td><td>248 (92 / 156)</td><td>248 (92 / 156)</td><td>236 (83 / 153)</td></tr><tr><td>Transceiver lanes</td><td>2 in CBG256; 4 in CBG484</td><td>2 in CBG256; 4 in CBG484</td><td>4</td><td>4</td><td>4</td></tr><tr><td>Speed grades</td><td>1 to 3</td><td>1 to 3</td><td>1 to 3</td><td>1 to 3</td><td>1 and 2</td></tr><tr><td>User flash memory (UFM)</td><td>not stated</td><td>not stated</td><td>105,472 kbit</td><td>105,472 kbit</td><td>not stated</td></tr><tr><td>Internal flash, total</td><td>not stated</td><td>not stated</td><td>not stated</td><td>256 Mbit</td><td>not stated</td></tr><tr><td>Configuration time</td><td>not stated</td><td>not stated</td><td>not stated</td><td>under 30 ms (Lattice claim)</td><td>not stated</td></tr><tr><td>Flash data retention at 100 °C junction</td><td>20 years</td><td>20 years</td><td>20 years</td><td>20 years</td><td>not stated</td></tr><tr><td>Flash programming cycles within retention spec (write/erase maximum)</td><td>10,000 (100,000)</td><td>10,000 (100,000)</td><td>10,000 (100,000)</td><td>10,000 (100,000)</td><td>not stated</td></tr></tbody></table></div><h3>Shared by all five Mach-N2 devices</h3><div><table><thead><tr><th>Spec</th><th>Value</th></tr></thead><tbody><tr><td>Platform and process</td><td>Lattice Nexus 2, TSMC 16 nm FinFET</td></tr><tr><td>Core supply</td><td>0.82 V</td></tr><tr><td>Transceivers</td><td>up to 16 Gb/s per lane</td></tr><tr><td>PCIe</td><td>hard Gen4 (16 GT/s) controller, up to x4, up to eight physical functions</td></tr><tr><td>Ethernet</td><td>10GbE, with PMA and PCS in hardware and the MAC in fabric</td></tr><tr><td>External memory</td><td>DDR4 and LPDDR4 up to 2400 Mb/s</td></tr><tr><td>Configuration</td><td>boots from internal flash (self-download mode); images programmed over JTAG or target SPI; no boot from external SPI flash</td></tr><tr><td>Image fallback</td><td>up to three stored images: primary, secondary and golden (Lattice); falls back on a failed authentication or a bitstream revision below the set minimum</td></tr><tr><td>Bitstream protection</td><td>AES-256-GCM encryption; ECDSA (up to 521-bit) or RSA (up to 4096-bit) authentication</td></tr><tr><td>Run-time cryptography</td><td>AES-256 engines at up to 2.5 Gb/s and 10 Gb/s; SHA-2, SHA-3 and HMAC up to 512 bits; ECDSA, ECDH and ECIES up to 521 bits; Ed25519; RSA 2048 to 4096; TRNG</td></tr><tr><td>Device identity</td><td>physically unclonable function (PUF), 256 bits of entropy, stable for more than 20 years; Lattice lists DICE and SPDM attestation on the PUF-derived identity</td></tr><tr><td>Anti-tamper</td><td>voltage and temperature monitor, plus user-triggered responses ranging from zeroising RAM and stored secrets to permanently disabling the device</td></tr><tr><td>Temperature grades</td><td>commercial 0 to 85 °C; industrial -40 to 100 °C</td></tr><tr><td>Power consumption</td><td>not stated</td></tr></tbody></table></div><h3>MH21D root-of-trust device: differences from the other four</h3><div><table><thead><tr><th>Spec</th><th>Value</th></tr></thead><tbody><tr><td>Post-quantum signatures</td><td>ML-DSA, LMS, XMSS, SLH-DSA</td></tr><tr><td>Post-quantum key exchange</td><td>ML-KEM</td></tr><tr><td>Other additions</td><td>Ed448; SHAKE128 and SHAKE256; crypto agility with field-updatable algorithms (Lattice)</td></tr><tr><td>ML-DSA and ML-KEM parameter sets</td><td>not stated (CNSA 2.0 requires ML-DSA-87 and ML-KEM-1024)</td></tr><tr><td>Secret storage</td><td>one-time-programmable memory; the battery-backed RAM option is not available</td></tr><tr><td>Provisioning</td><td>customer policy and key files plus an authenticated image, loaded over JTAG or target SPI before the first reboot</td></tr></tbody></table></div>Sources: [1][2][3][4][14][15][16]All Mach-N2 specifications are preliminary. Cell counts do not compare across generations: Nexus 2 system logic cells run about 1.63 per LUT against 1.2 for MachXO5-NX logic cells, so the 220k-cell MH20 has about 1.7 times the LUTs of the largest MachXO5-NX (our calculation).[2][9] Lattice quotes a boot time under 30 ms for the MH20, whose uncompressed bitstreams are 44 Mbit to 64.1 Mbit.[1][14] For CNSA 2.0 designs, the MH21D's parameter sets are a gating item; boot time and power only set budgets. Lattice's evaluation board carries an MH20, which lacks the PQC engines.[17]<h2> </h2>Recommended reading:<a href="https://www.wevolver.com/article/quantum-resistant-security-on-altera-fpga"> Post-quantum secure boot reaches low-cost and mid-range FPGAs</a>. How Altera placed PQC bitstream authentication in the Agilex 3 and Agilex 5 Secure Device Manager, and where other vendors put it in the boot chain.<h2>References</h2><ol><li><a href="https://www.businesswire.com/news/home/20260916542312/en/Lattice-Expands-Secure-Control-FPGA-Leadership-with-New-Lattice-Mach-N2-Family">Lattice Expands Secure Control FPGA Leadership with New Lattice Mach-N2 Family</a>, Lattice Semiconductor via Business Wire, September 16, 2026.</li><li><a href="https://www.latticesemi.com/view_document?document_id=54437">Lattice Nexus 2 Platform: Overview Data Sheet (FPGA-DS-02122, v0.80)</a>, Lattice Semiconductor, September 2026. Preliminary vendor datasheet.</li><li><a href="https://www.businesswire.com/news/home/20241210483055/en/Lattice-Advances-Low-Power-FPGA-Leadership-with-New-Small-and-Mid-range-FPGA-Offerings/">Lattice Advances Low Power FPGA Leadership with New Small and Mid-range FPGA Offerings</a>, Lattice Semiconductor via Business Wire, December 10, 2024.</li><li><a href="https://www.latticesemi.com/Products/FPGAandCPLD/Mach-N2">Mach-N2</a>, Lattice Semiconductor product page, accessed September 30, 2026.</li><li><a href="https://nvlpubs.nist.gov/nistpubs/SpecialPublications/NIST.SP.800-193.pdf">Platform Firmware Resiliency Guidelines (NIST SP 800-193)</a>, National Institute of Standards and Technology, May 2018.</li><li><a href="https://media.defense.gov/2022/Sep/07/2003071836/-1/-1/0/CSI_CNSA_2.0_FAQ_.PDF">The Commercial National Security Algorithm Suite 2.0 and Quantum Computing FAQ</a>, National Security Agency, December 2024. Cybersecurity Information Sheet, version 2.1.</li><li><a href="https://www.businesswire.com/news/home/20251013522544/en/Lattice-Launches-Industry-First-PQC-Ready-FPGA-Family-MachXO5-NX-TDQ">Lattice Launches Industry-First PQC-Ready FPGA Family: MachXO5-NX TDQ</a>, Lattice Semiconductor via Business Wire, October 13, 2025.</li><li><a href="https://www.latticesemi.com/view_document?document_id=54310">MachXO5-NX Family Root-of-Trust Devices Data Sheet (FPGA-DS-02120, v1.5)</a>, Lattice Semiconductor, August 2026. Vendor datasheet.</li><li><a href="https://www.latticesemi.com/view_document?document_id=53488">MachXO5-NX Family Data Sheet (FPGA-DS-02102, v2.3)</a>, Lattice Semiconductor, July 2026. Vendor datasheet.</li><li><a href="https://www.amd.com/en/blogs/2026/amd-spartan-fpga-grows-up-bigger-smarter-scalable-more-secure.html">AMD Spartan FPGA Grows Up: Bigger, Smarter, Scalable, More Secure</a>, AMD, June 15, 2026. Vendor blog.</li><li><a href="https://docs.amd.com/r/en-US/ug1283-bootgen-user-guide/Spartan-UltraScale-Authentication-Certificate">Spartan UltraScale+ Authentication Certificate (Bootgen User Guide, UG1283)</a>, AMD, June 2026. Vendor user guide.</li><li><a href="https://www.amd.com/content/dam/amd/en/documents/products/adaptive-socs-and-fpgas/vivado/configuration-flow-for-spartan-ultrascale-plus.pdf">Configuration Flow for AMD Spartan UltraScale+ Devices</a>, AMD, 2025. Vendor presentation.</li><li><a href="https://www.altera.com/newsroom/post-quantum-security">Altera Adds Post-Quantum Security to Agilex 3 and Agilex 5 FPGAs</a>, Altera press release, September 8, 2026.</li><li><a href="https://www.latticesemi.com/view_document?document_id=54443">Lattice Nexus 2 sysCONFIG User Guide (FPGA-TN-02370, v0.82)</a>, Lattice Semiconductor, September 2026. Preliminary vendor technical note.</li><li><a href="https://www.latticesemi.com/view_document?document_id=54436">Lattice Nexus 2 Platform: Specifications Data Sheet (FPGA-DS-02121, v0.80)</a>, Lattice Semiconductor, September 2026. Preliminary vendor datasheet.</li><li><a href="https://www.latticesemi.com/view_document?document_id=54471">Lattice Nexus 2 Multi-Boot User Guide (FPGA-TN-02385, v0.81)</a>, Lattice Semiconductor, September 2026. Preliminary vendor technical note.</li><li><a href="https://www.latticesemi.com/view_document?document_id=55346">Mach-N2 Evaluation Board (FPGA-EB-02078, v0.81)</a>, Lattice Semiconductor, September 2026. Vendor board guide.</li></ol>

Lattice's Mach-N2 FPGAs pair internal-flash boot with PCIe Gen4 and 16 Gb/s transceivers for compute and communications infrastructure.

Secure-control FPGA puts post-quantum root of trust on 215k-logic-cell device

Engineering motion systems for availability, serviceability, and lifecycle cost.

The Reliability Imperative: Why the Next Generation of AGVs Will Be Measured in Uptime, Not Speed

Jiaoyang Li (left) and Shuai Zhou (right) are developing LAMP, a system that helps teams of robots work together to move objects through cluttered spaces. The team also includes RI Ph.D. student Yorai Shaoul.Researchers from the Carnegie Mellon University School of Computer Science are developing a new way for teams of robots to work together to move objects through heavily cluttered spaces, where poor decisions can leave the robots stuck with no way forward.<iframe width="640" height="360" src="https://www.youtube.com/embed/XihghpMtPyI?&amp;t=2s&amp;wmode=opaque&amp;rel=0&amp;enablejsapi=1&amp;origin=https://www.wevolver.com" frameborder="0" class="fr-draggable">  </iframe>The work addresses a fundamental challenge in multirobot manipulation. Even when there’s a clear path from an object to its destination, obstacles may prevent the robots from reaching the positions they need to move it. This challenge is especially relevant in environments such as warehouses, where robots may need to work together to move objects through crowded spaces while navigating around shelves, equipment and other impediments.Long-Horizon Adaptive Manipulation Planning (LAMP) helps robots plan not only where an object needs to go, but also how they can work together to get it there. “LAMP is one example of the kind of robotics research being developed at Carnegie Mellon to make robots more capable of operating in complex, real-world environments,” said Jiaoyang Li, an assistant professor in the university’s Robotics Institute (RI).The planning system considers whether robots can reach the positions they need to be in to push or manipulate an object, navigate around obstacles, and coordinate their movements over a long sequence of actions. “We want the benefits of using multiple robots, such as needed stability, control and efficiency, but that comes at the cost of coordination,” said Shuai Zhou, a master’s student in the RI. “With LAMP, we plan the motions of the object and robots together, rather than treating them as separate problems.” LAMP combines learned models of how an object can be moved locally with search-based planning to find a path through the environment. The researchers call this approach LAMP-A*. The system generates possible local movements for manipulating the object and uses those movements in a global search to determine how the robots can move the object from its starting position to its destination.The team also developed LAMP-Lazy, a variation that avoids spending time verifying every possible movement before a task begins. Instead, it checks movements as they become necessary and can update its plan based on new information from the robot and its environment. <img src="https://s3-us-west-1.amazonaws.com/wevolver-project-images/froala%2F1790762123681-1790762123681.png" class="fr-fic fr-dib" />Jiaoyang Li (left) and Shuai Zhou (right) are developing LAMP, a system that helps teams of robots work together to move objects through cluttered spaces. The team also includes RI Ph.D. student Yorai Shaoul.“It’s kind of a feedback loop. We get new information about what happened and use that information to update the plan.” said RI Ph.D. student Yorai Shaoul. “That lets us respond to what’s actually happening in the environment and continue making progress toward the goal.” In testing, LAMP successfully completed multistep activities with sequential, interdependent actions that had challenged previous approaches. The researchers also tested the system in increasingly crowded environments, including a demonstration that spelled out the name of the conference where the work will be presented. The 2026 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS) will take place in Pittsburgh this fall. In the demonstration, multiple robots transported 12 objects individually to assemble the letters “IROS,” continually adjusting their plans as the workspace changed.“Our acceptance at IROS gives us an opportunity to share this approach with the broader robotics community, especially as we welcome researchers from around the world to Pittsburgh,” Li said. “It’s meaningful to present this work here, where the research began, and to share it with the robotics community coming to our city.”The research was partially supported by the National Science Foundation. Learn more about LAMP and the team’s work on the project website.

CMU Researchers Develop System That Helps Robots Collaborate in Crowded Spaces

LAMP Helps Robots Find a Way Through

Most engineering organizations ship something they would rather a competitor never saw. In cloud software, that code stays on a server the company controls. In embedded products, however, it does not, because the software that defines the product gets compiled, flashed, and handed to whoever buys the device.That gap carries a real price. The Institute for Employment Research (IAB) puts the economic damage from industrial and economic espionage at roughly $400 billion a year in the United States, about 2.1 percent of GDP, and around €200 billion in Germany. Its 2025 survey also found that 22 percent of German firms conducting research and development confirmed an espionage attack in the previous five years, compared with 8.3 percent of those without an R&amp;D function [1]. Innovation, in other words, attracts attention.Automotive is a particularly clear case. A single electronic control unit (ECU) can hold years of calibration work, a proprietary control algorithm, and cryptographic keys, all within one binary. This article looks at why that binary is exposed by default, what modern tooling can pull out of it, and how <a href="https://emproof.com/en/solution">Emproof's Nyx</a> hardens it in place.<img src="https://s3-us-west-1.amazonaws.com/wevolver-project-images/froala%2F1790776375099-Emproof_Binary-Protection_Automotive.jpg" style="width:100%px" class="fr-fic fr-dib" />Emproof Binary Protection for Automotive. Source: emproof<h2>The Binary Is the Real Attack Surface</h2>Firmware leaves the building through more doors than most teams count. Most microcontrollers expose a debug or readout interface, and over-the-air update packages can often be downloaded and unpacked [2]. Diagnostic interfaces sit on the vehicle bus. In automotive programs specifically, binaries also move routinely between Tier 1 suppliers and OEMs as a normal part of integration work.Once someone has the file, the tooling is free. Ghidra, the reverse engineering suite released by the US National Security Agency, disassembles the image, reconstructs control-flow graphs, and decompiles machine code into C-like pseudocode. Signature databases identify known library functions, while constant-finder plugins locate cryptographic routines by their lookup tables [2].In practice, an analyst can therefore find the function that validates a license, read the conditions gating a paid feature, or locate a hardcoded key by pattern rather than by luck. None of this requires access to the original source code.<h3>Why Readout Protection Is Not Enough</h3>Readout protection is a single barrier, and a hardware one at that. Fault injection, which glitches supply voltage or clock timing at precisely the right instant, can skip the check outright, while bootloader logic bugs and side-channel methods offer other ways in [2].It also guards only one path, doing nothing about an image pulled from an update server or shared with an integration partner. Meanwhile, the code underneath stays fragile, since roughly 70 percent of severe vulnerabilities at major technology companies trace back to memory-safety issues, and about 80 percent of embedded systems will continue to rely on C and C++ over the next decade.<h2>Large Language Models Lowered the Skill Barrier</h2>Decompilation was never the real bottleneck. Interpreting the output was always the slower and more expensive half of the job.Ghidra hands back pseudocode full of names such as FUN_0800a1c4 and undefined4 uVar7, and turning that into a working understanding of the code has traditionally required an experienced engineer and a considerable number of hours. That step is now largely automated. When decompiler output is fed to a capable large language model (LLM), the model will describe a function's purpose in plain English, propose meaningful variable names, annotate the control flow, and flag branches that resemble a licensing or safety check.The shift is economic rather than technical. Analysis that once cost expert-days now costs minutes, so an attacker can review far more binaries, and someone without deep reverse engineering experience can still obtain useful results. Complexity was never security, although it did reliably buy time, and that time is now shrinking.<h2><img src="https://s3-us-west-1.amazonaws.com/wevolver-project-images/froala%2F1790702404656-1790702404656.jpeg" width="624" height="367" class="fr-fic fr-dii" />Close-up of an electronic board with components. Source: AdobeStock. </h2><h2>What Emproof Nyx Does to the Compiled Binary</h2><a href="https://emproof.com/en/home">Emproof</a> is a German embedded security company, and Nyx is its binary transformation tool. It runs after compilation, directly on the binary, with no source code requirement and no hardware change. As a result, it can also be applied to third-party, legacy, and already-deployed firmware.<a href="https://emproof.com/en/nyx-microcontroller">Nyx Microcontroller</a> applies several layers of protection in a single pass:<ul><li>Control-flow obfuscation restructures the code layout so that decompiler output no longer mirrors the original program structure.</li><li>Secret hiding conceals keys and sensitive data held inside the image.</li><li>Anti-tamper checks the deployed image against a verified reference at startup, then triggers a response defined by the manufacturer, such as entering a safe state.</li><li>Anti-debug and anti-emulation techniques frustrate dynamic analysis on a live device.</li><li>Exploit mitigation adds stack canaries and control-flow integrity (CFI) to defend against memory-corruption attacks.</li></ul>Because these transformations rewrite the binary, correctness matters as much as protection. Emproof therefore preserves program semantics and uses formal methods, including translation validation, to prove that the transformed code behaves as the original did [3].<img src="https://s3-us-west-1.amazonaws.com/wevolver-project-images/froala%2F1790776477002-Emproof_Code-Hardening+Kopie.jpg" style="width:100%px" class="fr-fic fr-dib" />Source: emproof<h3>Overhead and Toolchain Integration</h3>Weight and runtime are the reasons embedded code so often ships unprotected. Emproof puts typical memory overhead for Nyx at 10 to 15 percent, and that figure is tunable. Engineering teams can protect the full image or scope transformations to specific modules, optimize each one for size or for speed, and exclude sections with hard real-time deadlines [3].For integration, the tool ships as a Docker container that drops into pipelines such as Jenkins, GitLab CI, GitHub Actions, and Azure DevOps, through a command-line interface (CLI) or a REST API. Analysis and transformation run entirely inside the customer's own infrastructure, and reproducible builds and delta testing keep the tool compatible with existing verification workflows.<h2>Why This Lands Hardest in Automotive</h2>Nyx Microcontroller covers the architectures that dominate automotive design, including Infineon AURIX (TriCore), Arm Cortex-M and Cortex-R, and Renesas RH850 [4]. The requirements tighten further in safety. A compromised braking or steering ECU is not only an intellectual property (IP) problem; it is a functional safety one. The enterprise edition of Nyx therefore carries ISO 26262 ASIL-D certification, the highest Automotive Safety Integrity Level, assessed by TÜV Nord, and it generates audit artifacts for safety documentation [4, 5]. One of the world's largest Tier 1 suppliers is a reference customer.Regulation pushes in the same direction. UNECE WP.29 R155 ties vehicle type approval to a certified cybersecurity management system [6], ISO/SAE 21434 defines the engineering process behind it [7], and the EU Cyber Resilience Act extends secure-by-design obligations to connected products more generally [8].<h2>Protection at the Binary Level Becomes the Baseline</h2>Firmware IP protection is shifting from a differentiator to an expectation. The binary was always readable, but what has changed is that reading it now takes hours instead of weeks, and regulators have started asking manufacturers what they did about it.Working at the binary level is what makes the answer practical, since it doesn't require rewriting, silicon changes, or recompiling of code a supplier may not even own, at an overhead small enough for devices that previously had no room for security at all. Emproof offers browser-based demos for engineers who want to see what the transformed output looks like.<hr /><h3>References</h3>[1] A. Glitz, S. Kohaut, and I. Möller, "Nine percent of businesses fall victim to espionage," IAB Short Policy Report, no. 2/2025, Institute for Employment Research, Nuremberg, Germany, May 2025. [Online]. Available: https://doku.iab.de/kurzber/2025/kb2025-02_en.pdf [2] Emproof, "Defend against the threat of reverse engineering with Emproof Nyx." [Online]. Available: https://emproof.com/en/reverse-engineering. [Accessed: Aug. 2, 2026].[3] Emproof, "Solution: Emproof Nyx." [Online]. Available: https://emproof.com/en/solution. [Accessed: Aug. 2, 2026].[4] Emproof, "Nyx Microcontroller." [Online]. Available: https://emproof.com/en/nyx-microcontroller. [Accessed: Aug. 2, 2026].[5] Emproof, "Emproof Nyx awarded ISO 26262 certification for functional safety in automotive components." [Online]. Available: https://emproof.com/news-posts/emproof-nyx-awarded-iso-26262-certification-for-functional-safety-in-automotive-components/. [Accessed: Aug. 3, 2026].[6] United Nations Economic Commission for Europe, UN Regulation No. 155 — Uniform provisions concerning the approval of vehicles with regards to cyber security and cyber security management system, Geneva, Switzerland, 2021.[7] ISO/SAE 21434:2021, Road vehicles — Cybersecurity engineering, International Organization for Standardization, Geneva, Switzerland, 2021.[8] European Parliament and Council of the European Union, Regulation (EU) 2024/2847 on horizontal cybersecurity requirements for products with digital elements (Cyber Resilience Act), Oct. 2024.

A modern vehicle's competitive advantage lies in compiled firmware. Binary-level protection secures that code without source access, hardware changes, or a heavy memory budget.

The Growing Cost of Embedded IP Theft and How Firmware Hardening Helps

Closing the latch on a tool isn't the end of a tool change. The controller needs to know that the tool-change mechanism closes correctly, register the new instrument, load its parameters, and decide if and when the next movement can safely occur. Similar situations occur elsewhere in the robot: a joint encoder is reporting its nominal position, even as the robot arm vibrates; a sensor that showed no noise on the test bench starts picking up interference next to a motor driver; and a power stage tucked into a miniature joint runs far hotter than expected. All of these are cases of the controller not receiving the information that it needs from the electronics to understand and control the system. The task is to understand what the robot and its various peripherals have to say to the controller, what different circuits say about the robot's condition, state, or planned activity, and what additional sensors or protection circuits could be useful in diagnosing a situation or preventing damage.<h2>Position Is Only Part of Motion</h2>A joint encoder may be able to report rotational position on a revolute joint, but it may not reveal link compliance or vibration elsewhere on the arm. A 6-axis inertial sensor mounted on the robot arm provides another perspective on motion.The Murata <a href="https://www.murata.com/en-us/products/sensor/gyro/overview/lineup/sch16t">SCH16T-K01</a> inertial sensor, for instance, includes a 3-axis gyroscope with bias instability down to 0.3°/h and noise density down to 0.4m°/s/√Hz, plus a 3-axis accelerometer.Two brief remarks are in order on this sensor. First, time synchronization allows the inertial measurements to be aligned with data such as the joint-encoder output. When combining the data, the system still must account for sampling, latency, and bandwidth. Cross-axis compensation and stable performance across temperature can reduce the need for calibration, but that benefit still depends on integration in the finished system. Second, it should be remembered that it does not directly provide the position of the end effector. The inertial sensor can supply answers to other questions that are relevant to determining or understanding motion, though.Feedback quality can also be a function of the motor-drive electronics. Multi-axis motor drives tend to be miniaturized, and decoupling capacitors can be exposed to board flex and vibration, while high-permittivity dielectrics can show a reduction in effective capacitance under DC bias that is not apparent from the nominal capacitance value.Murata's <a href="https://www.murata.com/products/capacitor/ceramiccapacitor">ceramic-capacitor range</a>, for instance, includes case sizes as small as the 008004 inch size (0.25×0.125mm), as well as soft- and metal-termination options intended to improve resistance to cracking under board flex and mechanical or thermal stress.What the surgical system is looking to detect at the business end of the instrument is a press, release, flex, or vibration; the <a href="https://www.murata.com/en-us/products/sensor/picoleaf/overview/basic/principle">Picoleaf</a> piezoelectric film sensor from Murata is 0.2mm thick or less and can fit in spaces where a rigid sensor package would be impractical, taking advantage of a different set of physics than a typical strain gauge.Picoleaf's output depends on the speed and direction of its deformation and requires careful consideration of mounting, circuitry, and mechanical connections to the business end in order to get useful information about the sensed event. The behavior of the sensor under temperature gradients is another easy pitfall, and one that is particularly relevant in an operating room.The tip of an instrument close to a surgical site can experience widely varying temperatures due to the patient's body heat, warmed irrigation fluid, and the resistive tissue heating produced by an electrosurgical unit. Temperature changes can generate an unwanted output in a pyroelectric film; Picoleaf is non-pyroelectric, which reduces that source of signal, although the finished sensing assembly still requires temperature validation.The <a href="https://pim.murata.com/en-us/pim/details/?productCategoryId=amrSensorMagneticSensor&amp;partNum=MRMS166R" target="_blank" rel="noopener noreferrer">MRMS166R AMR sensor</a> from Murata is a contactless magnetic switch in a 1.0 x 1.0 x 0.45mm package with typical current consumption of 20nA at 1.5V, low enough to suit a battery-powered instrument. However, for faster switching applications, Murata's MRMS543E is better suited.<h2>Keeping the Measurement Intact</h2>While the choice of a sensor is important, it is just one factor that must be considered in the design. Electrical noise on a robot arm can couple into nearby encoder and sensor wiring and cause a measurement error or lead the controller to report an incorrect state, such as an open latch or detached tool.Either can be serious, but an incorrect state can lead the controller to act on something that has not happened. The engineer should understand how the noise is coupling into the signal path and take that into account when applying filters or other noise-suppression features. A false state indication can be more serious than a noisy measurement, which is why the coupling paths should be identified before suppression components are selected. Filtering can help, but layout, routing, and the coupling path also matter. For surgical robotics, Murata’s EMI/inductor selection is a curated list that promotes the highest-reliability products from powertrain/safety grade components. For more information on this candidate list and policies, please reach out to your local Sales Rep. or Murata Sales contact.<a href="https://www.murata.com/en-us/products/emc/emifil/overview/lineup/bl">BLM-family chip ferrite beads</a> provide frequency-dependent impedance on selected power or signal lines to suppress conducted noise. Murata offers a broad range for different applications, as well as different sizes and current ratings. The component should be chosen considering the noise spectrum, current, signal bandwidth, and permissible waveform distortion level. For instance, for common-mode noise on a differential pair, an appropriately selected <a href="https://www.murata.com/en-us/products/emc/emifil/overview/lineup/cmcc">common-mode choke</a> can suppress common-mode current while minimally affecting the desired signal.Murata provides signal-line common-mode chokes for interfaces with data rates up to 12Gbps and separate power-line versions rated up to 18A, but an appropriate part has to be chosen for a particular application based on the interface specification, current requirements, noise spectrum, package, and operating temperature.What makes this approach actually practical is <a href="https://www.murata.com/en-us/tool/simsurfing/characteristics-viewer">SimSurfing</a>, Murata's online component-selection and simulation tool. Engineers can compare the frequency characteristics of candidate components, assess those data against measured noise spectra and signal bandwidths, and then verify the choice when prototyping.It's a vastly different process than having to desolder things and put on a generic filter after an EMC test has failed, and one that doesn't have to come with awkward questions from management if the wrong part is chosen.<h2>Isolation in the Space You Have</h2>There are at least two power supply challenges related to the surgical robot. The first is a supply for a local measurement or control circuit, which may require an isolated rail. The second is the mains AC supply for the equipment.For the local isolated rail, isolation voltage is only one parameter. Galvanic isolation removes the direct electrical connection, but fast common-mode current can still couple through parasitic capacitance across the barrier into sensitive secondary-side circuitry. The <a href="https://www.murata.com/en-US/news/power/isolated-dc-dc-converter/2025/0430">NXJ1T</a> isolated DC-DC converter from Murata provides 4.2kVDC HiPot test isolation in a 10.55 × 13.70 × 4.04 mm SMD package. Its low isolation capacitance helps limit that common-mode current.The NXJ1T employs the company’s proprietary block-coil transformer technology. Murata points out that some alternative solutions using wireless-power-coil architectures have lower coupling factors, operate at switching frequencies of the order of 10 MHz, and realize only 40–60% efficiency. The NXJ1T operates at a lower switching frequency of 500kHz to 2MHz and offers approximately 80% efficiency. It also provides common-mode transient immunity, enabling it to tolerate fast common-mode transients in a high-noise environment, such as a PCB with a switched-mode motor driver. However, the overall system’s noise immunity still has to be analyzed and verified during development.Meanwhile, the <a href="https://www.murata.com/en-eu/news/power/ac-dc-converters/2024/1121" id="isPasted">PQC600 AC-DC power supply</a> addresses the second challenge, the mains supply for the equipment. It delivers 600W with forced-air cooling (350W convection cooling), has a height of less than 1U, achieves 95% efficiency at full load, and is certified to IEC 60601 Ed.3 medical (2 x MOPP Pri-Sec; 1 x MOPP Primary-Chassis Ground, 1 x MOPP output to chassis). It also includes Applied Part Type B &amp; BF rated (isolation and patient leakage current performance). For lower power applications, there is also the PQC250, which provides 250W o/p power.The key difference between the two power supplies is that the locally mounted NXJ1T isolated DC-DC converter is employed to provide isolated rails for local signal conditioning circuits, while the PQC600 AC-DC power supply serves as a certified building block at the mains input.From the output of the isolated converter, pSemi-Murata provides several high-efficiency, low-profile charge-pump capacitor dividers to convert to stable, lower voltage levels - ideal for space-constrained applications, such as surgical robots. The <a href="https://psemi.com/products/power-management/pe25304/" target="_blank" rel="noopener noreferrer">PE25304</a> and <a href="https://psemi.com/products/power-management/flexicp-pe25204/" target="_blank" rel="noopener noreferrer">PE25204</a> step-down from 48V rails by dividing by 4 to provide a stable 12V@6A equipment supply, while the PE25208 divides by 2 or 3 from a 48V or 24V input with an output current of up to 10A. For 12V input voltage applications, the <a href="https://psemi.com/products/power-management/flexicp-pe25213/" target="_blank" rel="noopener noreferrer">PE25213</a> divides by 2 or by 3 to create a 6V or 4V rail, respectively, with a maximum of 10A. These can serve as the input to the point-of-load regulators provided by Murata’s Mono and Pico product families. For applications requiring high-current point-of-load conversion in a compact footprint, Murata’s MonoBK series of non-isolated DC-DC converters provides an efficient solution. The modules integrate key power-conversion functions into a small package, reducing external component count and simplifying PCB layout. This approach is particularly useful in surgical robotics, where high-performance processors, FPGA devices, imaging electronics, and motion-control circuits often require multiple low-voltage, high-current rails located close to the load. By placing efficient point-of-load regulation near these devices, designers can reduce distribution losses, improve transient response, and help manage thermal constraints inside compact electronic assemblies.<h2>Heat Has Nowhere To Go</h2>A small joint can create little space for the motor and power electronics. To install the sensor in an easily accessible place, it is not always possible to place it directly at the hottest spot. The controller may respond too late, or, conversely, the temperature of the entire casing may be used instead of the desired value.This can be solved by choosing the right sensor. Thanks to their miniaturized design, NTC thermistors from Murata in the <a href="https://www.murata.com/en-us/products/thermistor/ntc/overview/lineup/ncu">NCU series</a> can be used in tight mechanical structures. The smallest package in the series is 0.6 × 0.3mm. Some NCU03 parts have a 1% resistance tolerance and are rated for operation up to 125°C. Some 1.0 × 0.5 and 1.6 × 0.8mm variants, in turn, are rated for operation up to 150°C. Of course, the choice of thermistors also depends on the desired resistance, tolerance, and temperature. The complete range of options is indicated in the product specification.Thus, in a suitable measurement circuit, a properly selected thermistor mounted close to a winding or power stage can provide the controller with a more representative local temperature signal for its task: compensation, derating, warning, or shutdown. It is important to remember that the location of the sensor must be verified in the assembled circuit since placement in an inappropriate place will provide misleading results.<h2>A Change of Tool Also Involves Data</h2>Closing the latch is insufficient information for the robot to know which tool has been installed. By using appropriate magnets and mechanisms, an AMR switch could be used to sense either the latch or the attachment state. Then, a UHF reader could be used to read the tag's ID and contents. Host software could use the tool's identity to retrieve operating instructions, usage and reprocessing logs, or service records before proceeding, if needed.That is different from requiring a visual inspection, sterilization record, or clinical authorization. An optical code could be used to identify the instrument, but the reader must be able to see it. A different orientation or number of uses may hide useful markings; RFID removes the line-of-sight and marking-wear limitations, although orientation can still affect read performance. However, RFID implies a different set of requirements to be addressed: those of location, presentation, materials, and RF interactions.<h2>Item Identification </h2>Accurately identifying items in robotic automation systems has become increasingly important. Implementing a successful RFID (Radio Frequency Identification) system is an accurate and efficient method for keeping track of these items. When an RFID tag is applied to an individual item, the tag often remains a permanent fixture on that device. Not only does this allow this item to be correctly identified, but when integrated with the host system, additional information can be quickly realized, such as total time usage, processing logs, operating instructions, and item calibration.Murata’s UHF Micro tag series is available in two sizes (as small as 1.2 × 1.2 × 0.55mm), where the smallest HF/NFC tag measures only 3.2 x 3.2 x 0.7mm. All micro tags are designed with an integrated antenna that is compatible with an over-molding process. Read range performance is typically 20 ~ 30mm, which is ideal for individual product identification.Mounting RFID tags on metal poses a bigger challenge than on other materials because nearby metal can limit the performance of a conventional RFID tag. Murata’s<a href="https://www.murata.com/en-us/products/rfid/rfid/overview/lineup/uhf/metal"> LXTBKZMCMG-010 on-metal tag</a> is designed to be applied to a metal object and utilizes the metal surface as a booster antenna. The tag measures 6.0 × 2.0 × 2.3mm, and Murata specifies a reference read range of up to 1.5m on metal at 4W EIRP. Performance will depend on the placement of the tag and RF environment. It’s always recommended that the user validate the device under the conditions it will be used in; this includes reprocessing, sterilization, temperature, and so on.The 2EG offers onboard and supported external antenna options, while the module-level radio approvals, test documentation, and design support from Murata help shorten the RF design-in cycle. The 48MHz Arm Cortex-M33 MCU core can run application code, whereas CryptoCell 312 can support cryptographic functions. Nevertheless, these capabilities are not sufficient to ensure security and reliability on their own. The application software, its updates, security, and antenna and radio configuration, as well as wireless coexistence, end-product radio and EMC approvals, and any applicable hospital-network integration, are the responsibility of the host equipment manufacturer.<h2>Where the Evidence Has To Come From</h2>At this point, component data has done its job: it has winnowed the options down. However, it is not a safety case. <a href="https://webstore.iec.ch/en/publication/89957">IEC 80601-2-77</a>, the standard for basic safety and essential performance of robotically assisted surgical equipment and systems, includes specific requirements for electromagnetic emissions and immunity. <a href="https://webstore.iec.ch/en/publication/67554">IEC 60601-1-2</a> covers electromagnetic compatibility (EMC) at the equipment and system level.For EMC, the power supply, sensor lines, motor-drive electronics, and wireless links can’t be evaluated in isolation. They have to be evaluated and tested in the final equipment or system configuration against the applicable EMC requirements for the intended-use environment.The wider validation plan must cover relevant system and subsystem configurations, including the temperature gradients, cable configurations, loads, fault conditions, and wireless-coexistence environments the equipment is likely to encounter. Similarly, medical instruments and assemblies subjected to cleaning and sterilization have to be validated for the intended reprocessing methods and number of cycles.Murata’s contribution to the safety case is more limited, but no less important. The block-coil construction of its isolated DC-DC converter offers specified isolation in a compact package with low capacitance across the isolation barrier. Its RFID portfolio includes microtags for embedding in molded parts, and a tag that can be mounted directly on metal. With <a href="https://www.murata.com/en-us/tool/simsurfing/characteristics-viewer">SimSurfing</a>, engineers can access characterized data on components to help identify candidates for noise suppression before measuring noise spectra on a prototype that incorporates them. Murata can also help evaluate RFID mounting options and RF performance.These are contributions worthy of consideration, but they are still contributions. The ultimate responsibility for obtaining the evidence needed to demonstrate compliance belongs to the manufacturer of the completed surgical robot. The manufacturer must also confirm with Murata that each selected part is suitable for the intended medical use.<hr /><h3>Reference</h3>Murata Manufacturing Co., Ltd. (2026). <a href="https://www.murata.com/en-us/campaigns/surgical-robotics">Application Guide: Surgical Robotics</a>. February 2026.

Surgical robotic controllers require comprehensive data and design to safely operate.

What the Controller Doesn't Know: Designing Electronics for Surgical Robotics

Transport logistics networks are becoming increasingly complex as global freight movement, rail operations, warehouse management, and distribution networks now involve multiple assets, locations, and stakeholders that must all operate together seamlessly. At the same time, businesses expect faster deliveries, improved reliability, and greater transparency across supply chain operations.One of the biggest challenges facing modern logistics is limited visibility across transportation assets. Companies often struggle to track containers, trailers, pallets, and other equipment throughout different stages of movement. These visibility gaps can lead to delays, asset downtime, inefficient utilization, and additional operational effort.Traditional logistics management often relies on delayed updates and manual coordination. The industry is now moving toward connected systems that provide real-time information through <a href="https://www.gi-de.com/en/digital-security/connectivity-iot/end-to-end-asset-tracking">IoT-enabled tracking</a>, digital visibility platforms, and connected supply chain solutions. This shift allows organizations to move from reacting to problems to making proactive, data-driven decisions [1].<img src="https://s3-us-west-1.amazonaws.com/wevolver-project-images/froala%2F1790618923560-1790618923560.jpeg" width="521" height="291" class="fr-fic fr-dii" />Supply chain truck, freight logistics, transportation cost. Source: AdobeStock.<h2>The Hidden Cost of Limited Asset Visibility</h2><h3>Operational Challenges</h3>Limited asset visibility creates challenges across logistics operations. When companies cannot quickly locate their containers, trailers, or other transport assets, teams spend additional time searching for equipment and coordinating manually. This reduces operational efficiency and increases the complexity of daily logistics management.Communication between warehouses, carriers, and logistics partners also becomes more difficult when accurate information is unavailable. A lack of real-time data can delay responses to unexpected disruptions and make it harder to manage changing transportation conditions [2].<h3>Financial Impact</h3>Poor visibility creates financial pressure. Organizations that under-utilize their assets may require additional backup assets because equipment is not being used efficiently or cannot be located when required. Idle assets, inefficient movements, and manual tracking activities can increase operational costs.Limited visibility can also affect customer experience. Delays, inaccurate delivery information, and reduced shipment transparency can impact customer confidence and service reliability [3]. On the other hand, real-time visibility can be advantageous to a business’s customer service capabilities.<h3>Supply Chain Impact</h3>Complex supply chains depend on accurate information. Without visibility into asset movement and availability, organizations face difficulties with capacity planning, identifying bottlenecks, and improving logistics decisions.Real-time asset information provides the foundation for understanding how resources are used and where improvements can be made.<img src="https://s3-us-west-1.amazonaws.com/wevolver-project-images/froala%2F1790618923565-1790618923565.jpeg" width="513" height="286" class="fr-fic fr-dii" />Global logistics network with real-time asset tracking. Source: AdobeStock.<h2>Why Real-Time Visibility Is Becoming a Logistics Priority</h2><h3>Moving Beyond Traditional Tracking</h3>Traditional tracking methods mainly provide location information, but modern logistics operations require deeper operational insight. Companies need to understand not only where assets are located but also their movement, availability, and condition, as well as how they affect overall supply chain performance.The transition from manual tracking methods to IoT-based solutions enables logistics teams to access real-time information and make faster decisions. This helps organizations identify potential disruptions earlier and respond before they affect operations [4].<h3>Key Visibility and Performance Metrics</h3>Real-time visibility becomes valuable when organizations can measure and analyze operational performance. Important visibility and performance indicators include:<ul><li>Asset location accuracy </li><li>Asset utilization rate </li><li>Transit time performance </li><li>Delivery reliability </li><li>Asset availability </li><li>Idle time measurement </li><li>Movement history analysis </li><li>Operational efficiency improvements </li><li>Cost per shipment or transport cycle </li></ul>These metrics help organizations understand how effectively they manage transportation assets. Accurate visibility data allows companies to identify inefficiencies, improve planning, and make better decisions across logistics operations.<h3>Business Impact of Real-Time Visibility</h3>Real-time asset visibility creates benefits beyond tracking. Better information supports improved logistics planning, more effective resource allocation, reduced asset downtime, and stronger supply chain resilience.Organizations can also improve forecasting accuracy, increase customer transparency, and support sustainability objectives by using transportation resources more efficiently and reducing unnecessary activities.Connected visibility platforms allow companies to manage assets more effectively and improve operational transparency. Better information can help organizations optimize transportation resources, improve customer communication, and support sustainability goals through more efficient operations [5].<img src="https://s3-us-west-1.amazonaws.com/wevolver-project-images/froala%2F1790618923570-1790618923570.jpeg" width="537" height="293" class="fr-fic fr-dii" />IoT asset tracking system. Source: AdobeStock.<h2>Building Smarter Transport Networks Through IoT Asset Tracking</h2><h3>Connected Asset Tracking Systems</h3><a href="https://www.gi-de.com/en/digital-security/connectivity-iot/end-to-end-asset-tracking">IoT-enabled asset tracking systems</a> are becoming a foundation for smarter logistics operations. By combining sensors, connectivity, and digital platforms to provide real-time visibility into transportation assets. These systems allow organizations to monitor containers, vehicles, pallets, and other transport equipment while gaining insights into asset location, movement, condition, and availability. Accurate asset information helps logistics teams make faster decisions, improve coordination, and manage transportation resources more effectively [5]. G+D’s IoTgoⓇ Asset Tracking solutions support connected asset visibility by enabling organizations to monitor and manage assets across modern logistics environments [2].<h3>Data-Driven Logistics Operations</h3>Real-time visibility creates value when organizations convert tracking data into operational insights. Analyzing asset movement patterns helps identify inefficient processes, improve equipment utilization, respond faster to disruptions, and strengthen coordination among logistics stakeholders [3]. Access to reliable operational data enables companies to improve planning, optimize resource allocation, and make informed decisions that enhance supply chain performance<h2>Improving Logistics Efficiency Through Real-Time Asset Visibility</h2><h3>IoT-Based Logistics Visibility</h3>Connected visibility solutions are becoming increasingly important in modern logistics operations as organizations seek better control over complex transportation networks. Real-time asset information helps companies optimize resource usage, reduce unnecessary movements, improve operational transparency, and support more efficient logistics processes. These capabilities allow organizations to respond more effectively to changing supply chain requirements while improving overall operational performance [2].<h2>Improving Rail Freight Through Digital Visibility</h2><h3>Making Rail Transportation More Efficient</h3>Rail freight networks involve complex routes, distributed assets, and coordination between multiple stakeholders. Limited information availability can make it difficult to monitor freight assets, plan operations effectively, and respond quickly to changing conditions.Digital visibility solutions help rail operators track freight assets throughout transportation routes and improve coordination with logistics partners. Better access to real-time information supports improved planning, increased efficiency, and more reliable freight operations [6].<h2>Boosting Supply Chain Visibility and Operational Performance</h2><h3>Improved Asset Utilization</h3>Transportation assets often move through multiple locations and operational stages, making efficient management challenging. Real-time visibility allows logistics teams to understand asset availability, identify gaps in equipment allocation, and improve how assets are assigned across operations. This supports better utilization of existing resources and reduces dependency on additional equipment [3].<h3>Reducing Costs and Improving Sustainability</h3>Operational inefficiencies often result from limited information about asset movements, delays, and resource usage. Visibility solutions help organizations identify where improvements can be made, enabling more efficient planning, reducing avoidable activities, and supporting sustainability efforts through improved resource management [2]. <h3>Enhancing Customer Experience</h3>Customers increasingly expect accurate information about shipment progress and delivery status. Real-time visibility enables logistics providers to share more reliable updates, improve communication, and provide greater transparency throughout the transportation process [3]. <h2>The Future of Transport Logistics: From Visibility to Predictive Intelligence</h2>The future of transport logistics is moving beyond tracking assets toward predicting logistics outcomes. Real-time visibility provides the foundation for combining IoT, analytics, automation, and artificial intelligence to support smarter decision-making.Operational data can help organizations identify patterns, predict potential delays, and improve response strategies before disruptions affect supply chain performance. These capabilities can create more flexible and resilient logistics networks, making real-time asset intelligence an increasingly important competitive advantage [1].<h2>Conclusion</h2>Transport logistics performance is increasingly measured through visibility, reliability, and operational intelligence. Asset tracking solutions provide the foundation for connected supply chain management by helping organizations understand where assets are, how they are being used, and where improvements can be made.Real-time data enables companies to improve efficiency, reduce operational challenges, and increase supply chain reliability. Solutions such as <a href="https://www.gi-de.com/en/digital-security/connectivity-iot/end-to-end-asset-tracking">G+D’s IoTgo® Track-Solar, Track-Fleet, and Smart Label</a> help organizations strengthen asset visibility across different logistics environments by supporting connected tracking and data-driven asset management. Future logistics networks will depend on accurate visibility, predictive capabilities, and connected asset management solutions to meet the demands of modern transportation operations. <hr /><h3>References</h3><ol><li>Transit Tomorrow  Sharath Muddaiah On Why Real-Time Asset Visibility Is Transforming Modern Logistics https://transittomorrow.com/sharath-muddaiah-real-time-asset-visibility/</li><li>Giesecke+Devrient (G+D) — IoT Logistics Visibility Cuts Costs &amp; Emissions https://www.gi-de.com/en/spotlight/digital-discoveries/iot-logistics-visibility-cuts-costs-emissions</li><li>Giesecke+Devrient (G+D) — Boosting Supply Chain Visibility and Efficiency https://www.gi-de.com/en/spotlight/digital-discoveries/boosting-supply-chain-visibility-and-efficiency</li><li>Giesecke+Devrient (G+D) — IoT Asset Tracking Solutions https://www.gi-de.com/en/digital-security/connectivity-iot/end-to-end-asset-tracking</li><li>Giesecke+Devrient (G+D) — Smart Logistics and Asset Tracking Solutions https://www.gi-de.com/en/industries/transport-logistics/transportation-logistics-services</li><li>Giesecke+Devrient (G+D) — Visibility Makes Rail Freight More Efficient https://www.gi-de.com/en/spotlight/digital-discoveries/visibility-makes-rail-freight-more-efficient </li></ol>

Engineering smarter logistics through asset visibility, operational intelligence, and connected tracking systems.

The Future of Transport Logistics: How Real-Time Asset Visibility Is Transforming Supply Chains

<h2 id="isPasted">The AI Moment in Embedded Software</h2>There is a gap between the industry narrative of what AI can achieve and the actual constraints of what engineers realistically face. Leaders and the media describe models that can reason, plan, and act with almost total autonomy, while engineers face serious real-world engineering challenges such as code certification, legacy code, and trustworthy AI analysis. This is where most of the authentic conversation about AI in embedded systems happens.The current development of AI solutions in embedded software is following two distinct paths. The first path is how AI is being applied when embedded software is built, for example through code generation assistants, static analysis tools, or test generation. AI is already performing well in this domain, because the constraints are the same ones that have governed software tooling for decades. AI is good at maintaining accuracy, traceability, and compliance. TASKING has decades of <a href="https://www.tasking.com/products/#compiler-toolsets">compiler and IDE development</a> focused on driving correct, efficient code, which is a natural foundation for AI-assisted tooling.At the same time, stakeholders and industry marketers promote a vision that is heavily focused on on-device deployment, such as running complex AI models directly on embedded targets. However, on-device AI in safety-critical systems remains in its early stages. Not every microcontroller requires a neural network or an LLM; in fact, much of what is labeled "AI-enabled" in production today is classic signal processing or a well-tuned control loop under a modern marketing label. While on-device inference is progressing, tools, verification workflows, and AI-assisted development productivity are advancing far more rapidly.<h2><img src="https://s3-us-west-1.amazonaws.com/wevolver-project-images/froala%2F1790615447989-1790615447989.png" width="624" height="416" class="fr-fic fr-dii" />IC7 Mini on the desk. Source: TASKING.Understanding the Engineering Tradeoffs Nobody Can Skip</h2>Embedded engineers have always worked inside the following dimensions: performance, power, memory, and cost. AI adds a fifth dimension that doesn’t sit neatly alongside the other four. Every gain in model capability tends to cost latency, power, or memory, and sometimes all three.Deploying neural networks on embedded targets requires adapting models to run efficiently within kilobytes of RAM and flash memory. Standard techniques like model pruning and quantization reduce execution precision to lower footprint, but achieving real-time performance on accelerators like vector DSPs depends on toolchain-level optimizations. TASKING’s compiler and tooling ecosystem support this deployment pathway through advanced compiler scheduling, vectorization libraries, efficient memory tiling with DMA transfers, and hardware tracing tools like the <a href="https://www.tasking.com/products/bluebox/ic7pro-bluebox/" target="_blank" rel="noopener noreferrer">iC7 pro</a>—enabling up to a ~70x inference speedup on specialized architectures like the Infineon® AURIX™ TC4x.Consider a vibration-monitoring node for predictive maintenance. A float32 network works well in a cloud prototype, but the deployed device has a small RAM budget and must run for years on a battery. An int8 model with fewer layers, fed by conventional feature extraction, may score slightly lower on benchmarks and still be the better system: predictable timing, lower power, simpler validation, and a viable bill of materials.Safety requirements add another layer. For a fixed model graph, inference time is usually quite predictable. More difficultly, outputs are statistical rather than derived from a requirement, which complicates verification, and that timing can still vary with memory contention on multicore devices. Automotive and industrial projects under <a href="https://www.iso.org/standard/68383.html">ISO 26262</a> and <a href="https://webstore.iec.ch/en/publication/5515">IEC 61508</a> still need bounded execution time, bounded memory, controlled failure modes, and auditable evidence. Moreover, <a href="https://webstore.ansi.org/standards/iso/isopas88002024">ISO/PAS 8800:2024</a> addresses AI in road vehicles more specifically.In this landscape, the toolchain matters here for a concrete reason. Model converters and inference libraries emit C or C++ that a compiler turns into the final binary. Optimization quality, code-size control, debug visibility, and timing analysis then decide whether the model fits and meets its deadlines. As models shrink to fit hardware, this stage matters as much as the model architecture. TASKING's qualified compilers and libraries are built for it.TASKING’s toolchain provides compelling value propositions for embedded software engineers. The company offers a strong safety and security ecosystem, which includes certified code-generation tools and libraries. At the same time, TASKING’s broader offerings span debug, trace, test, static analysis, automated testing, structural coverage, and requirements traceability.<a href="https://www.tasking.com/products/smartcode-aurix-tc4x/" target="_blank" rel="noopener noreferrer"><img src="https://s3-us-west-1.amazonaws.com/wevolver-project-images/froala%2F1790615447996-1790615447996.png" width="458" height="308" class="fr-fic fr-dii" />SmartCode, Software development environment of certified compiler toolsets for Infineon AURIXTM TC4x microcontrollers.  Source: TASKING.</a><h2>AI in Embedded Software Through TASKING's Lens</h2>Everyone involved in the embedded software industry is working through what AI means for their products, and TASKING is no exception. Across their portfolio, that work shows up as exploration into smarter static analysis, AI-assisted development workflows, and tooling built to handle embedded AI targets. These tools are ongoing work, rather than a finished product line. What stays consistent for TASKING is the underlying discipline. TASKING's compiler, debugger, and test &amp; verification tools exist to produce code that is efficient, traceable, and certifiable, and any AI capability layered onto that portfolio must serve those same goals. Smarter static analysis that catches defects earlier is valuable because it strengthens the certification case, not because it makes the tooling sound more advanced.AI won't replace deterministic engineering disciplines in embedded systems, and no credible toolchain vendor should suggest otherwise. But what AI will do is change the workflows engineers use to write, verify, and optimize code. TASKING is working to provide engineers with the skill set embedded teams need to keep up. TASKING is a partner for embedded teams navigating the transition, not another voice adding to the hype of idealized, unrealistic AI solutions.AI is changing how embedded software has traditionally been developed, and a trusted, integrated toolchain is what makes the actual difference within this shift. Explore <a href="https://www.tasking.com/compile-debug-test/">TASKING's integrated toolchain for AI-ready embedded development</a> to see what that looks like in practice.

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