<p id="isPasted">Embedded vision systems are evolving quickly, and with that evolution comes a shift in how designers approach system architecture. Cameras are now part of complex pipelines that include multiple sensors, interface bridges, real-time preprocessing, and edge artificial intelligence (AI) inference. As these elements converge, designers deliver more capability with smaller form factors and tighter power budgets.</p><p>Low-power field-programmable gate arrays (FPGAs) are emerging as efficient aggregation points for camera inputs and sensor data. They can bridge diverse interfaces, manage data flows, and perform early-stage processing without the overhead and latency of a full system-on-chip (SoC).</p><p>In this week’s New Tech Tuesdays, we explore how low-power FPGAs are reshaping embedded vision architectures, why they are gaining traction, and what designers can expect as edge systems continue to evolve.</p><h2>From Single Sensors to Interface-Heavy Vision Systems</h2><p>The growth of embedded vision is driven by demand for intelligent endpoints, from smart cameras and industrial inspection systems to human-machine interfaces (HMIs). As more processing moves to the edge, sending raw video streams to the cloud becomes less practical because of latency, bandwidth, and privacy concerns.</p><p>At the same time, sensor ecosystems have become more fragmented, requiring designers to support Mobile Industry Processor Interface Camera Serial Interface 2<sup>®</sup> (MIPI CSI-2), Universal Serial Bus (USB), low-voltage differential signaling (LVDS), and other standards within a single system. Traditionally, bridging these interfaces required multiple chips or a large SoC, increasing power consumption and design complexity.</p><p>Low-power FPGAs address this challenge by serving as flexible glue logic and preprocessing engines. Unlike fixed-function application-specific integrated circuits (ASICs) or high-power SoCs, FPGAs enable designers to customize data paths and adapt to evolving requirements without redesigning hardware. They can manage multiple input streams, synchronize sensors, and perform tasks such as image scaling or filtering while maintaining deterministic latency and low power consumption. As edge AI moves inference closer to the device, FPGA-based aggregation is bringing control and preprocessing closer to the sensor layer.</p><h2>Scaling Edge Vision Without Scaling Power</h2><p>As embedded vision evolves, the role of low-power FPGAs is expanding.</p><p>One trend is tighter integration with AI accelerators. FPGAs can serve as front-end processors that condition and route data efficiently into neural processing units (NPUs) or microcontrollers, reducing downstream workloads by sending selected, preprocessed data to the inference stage.</p><p>Power efficiency will also remain critical for always-on applications such as smart cameras, gesture recognition systems, and industrial monitoring devices. These use cases require architectures that remain responsive while minimizing standby and active power draw.</p><p>Another key direction is modularity and rapid prototyping. Designers need platforms that expose camera interfaces, support debugging, and allow quick iteration. System-on-module (SoM) platforms are enabling this shift by providing pre-integrated hardware blocks that accelerate development for smart endpoints and vision appliances.</p><p>Finally, scalability will continue to shape adoption. Designers need solutions that can evolve with their applications—from simple sensor aggregation to more advanced preprocessing—without requiring a complete system redesign.</p><h2>The Newest Products for Your Newest Designs<sup>®</sup></h2><p>For developers building low-power embedded vision systems, the <a href="https://www.mouser.com/en/new/lattice-semiconductor/lattice-crosslinku-nx-som-board" target="_blank">Lattice Semiconductor CrossLinkU-NX SoM board</a> offers a flexible and efficient platform for rapid prototyping and deployment. Built around Lattice’s low-power FPGA architecture, this SoM simplifies interface-heavy designs while maintaining tight power budgets. Its low-power FPGA enables designers to aggregate and manage multiple image streams without relying on a higher-power SoC, providing efficient data routing with predictable latency and low energy consumption.</p><p>The platform also supports common vision and connectivity interfaces, making it easier to bridge disparate sensor standards within the same design. This is particularly valuable in applications that combine multiple cameras or require compatibility across evolving interface ecosystems. Combined with integrated memory and high-speed input/output (I/O), the SoM can efficiently buffer and transfer preprocessing image data in real time, helping maintain throughput in multi-sensor environments.</p><h2>Conclusion</h2><p>Embedded vision has evolved beyond image capture to encompass the management of complex, interface-rich data pipelines at the edge. Low-power FPGAs serve as efficient aggregation and preprocessing hubs, giving designers the flexibility to build adaptable systems without sacrificing power or performance.</p><p>As edge devices continue to demand more intelligence in smaller footprints, these programmable FPGA-based solutions will play a central role in shaping the future of vision-enabled systems.</p>

Explore how low-power FPGAs enable efficient embedded vision by aggregating sensor data, preprocessing images, and supporting edge AI with low latency.

Low-Power FPGAs Enable Embedded Vision at the Edge

<h2 id="isPasted">September 28th 2026 Efinix announced the Sapphire RV64 soft SoC</h2><p>The Sapphire RV64's CPU cores, caches and peripherals are built from FPGA logic, with DRAM reached through the FPGA's hardened DDR interface. It uses one to four cores derived from VexiiRiscv, an MIT-licensed open-source RISC-V CPU. Each core has a seven-stage in-order pipeline implementing RV64IM with optional A, F, D, C, Zba, Zbb, Zbs and Zicbom extensions; Efinix lists Linux support via an optional Sv39 MMU.<sup>[1][2][3]</sup></p><p><strong>Efinix aims it at designs that have "outgrown the performance, addressable memory, cache, and I/O limits of 32-bit embedded cores".</strong> Support covers all Efinix's Titanium and Topaz FPGAs (its 16 nm families) and Trion devices (its first-generation 40 nm family) from the T20 up.<sup>[1][4][5]</sup></p><h2>Why it matters</h2><p>The step from the company's 32-bit Sapphire SoC is mostly about memory. The 32-bit version addresses up to 3.5 GB of DRAM and has L1 caches only. Sapphire RV64 addresses up to 8 GB of DDR3 or LPDDR4x and adds a shared 64 to 512 KB L2 cache.<sup>[2][6]</sup> With the L2 enabled, it also keeps two AXI DMA ports from user logic coherent, so accelerators in the fabric share cached memory without software flushes.<sup>[2]</sup></p><p>The 32-bit Sapphire already runs Linux; Efinix's br2-efinix Buildroot tree now builds Linux 6.6 for Sapphire RV64 too, so far only for the Titanium Ti375 C529 development board.<sup>[7][8]</sup> The gain is address reach: Sv39 gives software a 512 GB virtual address space, and the physical map places 8 GB of DRAM and a 64 GB cached AXI window above the 4 GB a 32-bit address spans.<sup>[2]</sup></p><p>Raw speed is modest. On the Ti375 board one Sapphire RV64 core scores 1.23 to 1.57 CoreMark/MHz, and fMAX is 250 to 278 MHz on the Ti375 and 65 to 77 MHz on a Trion T120. On that T120, the nearest published 32-bit Sapphire configuration reaches 115 MHz in 7,391 logic/adders, against 77 MHz and 10,741 for the most basic 64-bit build.<sup>[2][9]</sup> The Ti375 also carries a hardened quad-core 32-bit RISC-V block, which Efinix benchmarks at 2.345 CoreMark/MHz at 1 GHz.<sup>[10][11][12]</sup> Multiplying score by clock (our calculation, if per-MHz scores hold across clocks and compilers), the best soft configuration gives about 400 CoreMark per core, a hard core about 2,300.</p><p>Where a hard CPU exists, <strong>Sapphire RV64's case rests on memory reach: up to 8 GB of DRAM</strong> against the hard block's 3.7 GB, and two cache-coherent DMA ports against its one AXI slave. It fits best on Trion, on Titanium and Topaz parts without the hardened block, and in 32-bit Sapphire designs that need more memory.<sup>[2][12][13]</sup></p><p>AMD's MicroBlaze V soft core already offers a 64-bit Sv39 implementation, with a Linux preset listed at 199 to 258 MHz on UltraScale+ devices; Lattice's RISC-V RX is 32-bit.<sup>[14][15][16]</sup></p><h2>Technical specifications</h2><h3>Sapphire RV64 SoC: configurable range</h3><div><table><thead><tr><th><p>Spec</p></th><th><p>Value</p></th></tr></thead><tbody><tr><td><p>CPU</p></td><td><p>1 to 4 VexiiRiscv cores, 7-stage in-order pipeline, little-endian; machine and supervisor modes</p></td></tr><tr><td><p>ISA</p></td><td><p>RV64IM; optional A, F, D, C, Zba, Zbb, Zbs, Zicbom</p></td></tr><tr><td><p>System clock setting</p></td><td><p>20 to 400 MHz (achieved clock limited by device fMAX)</p></td></tr><tr><td><p>L1 cache</p></td><td><p>Instruction and data, 1, 2, 4 or 8 ways of 4 KB each; write-back data cache</p></td></tr><tr><td><p>L2 cache</p></td><td><p>Optional, shared, 64, 128, 256 or 512 KB, 8-way; coherency point for DMA</p></td></tr><tr><td><p>On-chip RAM</p></td><td><p>4 to 512 KB, with SPI flash boot loader</p></td></tr><tr><td><p>External memory</p></td><td><p>DDR3 at 800 Mbps, LPDDR4x at 3,200 Mbps, HyperRAM at 500 Mbps; 4 MB to 8 GB; DDR requires the FPGA's hardened DDR controller (Trion's supports DDR3, LPDDR3 and LPDDR2)</p></td></tr><tr><td><p>Memory bus</p></td><td><p>AXI4 full-duplex or AXI3 half-duplex, 32 to 512 bits</p></td></tr><tr><td><p>User-logic ports</p></td><td><p>Up to 2 coherent AXI4 slave (DMA) ports, 32 to 512 bits; up to 2 AXI4 master ports: A (AXI-Lite compatible, 256 MB uncached I/O region) and B (burst-capable, 64 GB cached region)</p></td></tr><tr><td><p>Memory management</p></td><td><p>Optional Sv39 MMU; optional PMP at 4 KB granularity</p></td></tr><tr><td><p>Interrupt handling</p></td><td><p>PLIC and CLINT; direct-mode trap vectors only (no vectored mode)</p></td></tr><tr><td><p>Other options</p></td><td><p>FPU (single or single plus double precision); BTB, RAS and gshare branch predictor; hardware and software prefetchers; custom-instruction interface with 1,024 IDs</p></td></tr><tr><td><p>Peripherals</p></td><td><p>Up to 32 GPIO, 5 I2C, 3 SPI, 3 UART, 3 timers, 8 user interrupts, 5 APB3 slave ports; watchdog</p></td></tr><tr><td><p>Debug</p></td><td><p>RISC-V debug specification through the FPGA's JTAG User TAP, up to 4 hardware breakpoints, co-debug with the FPGA debugger; no GPIO-based soft debug TAP</p></td></tr><tr><td><p>Linux support</p></td><td><p>br2-efinix Buildroot tree: Linux 6.6, U-Boot 2025.01, OpenSBI 1.6; RV64 build for the Titanium Ti375 C529 development board</p></td></tr><tr><td><p>Supported FPGAs</p></td><td><p>All Titanium and Topaz; Trion T20 and above</p></td></tr><tr><td><p>License terms and price</p></td><td><p>Not stated</p></td></tr></tbody></table></div><h3>Sapphire RV64 single-core benchmark configurations (Efinix's Efinity design software, version 2026.1)</h3><div><table><thead><tr><th><p>Spec</p></th><th><p>Basic L1</p></th><th><p>Basic L2</p></th><th><p>Advanced L1</p></th><th><p>Advanced L2</p></th></tr></thead><tbody><tr><td><p>CoreMark/MHz (Ti375 board)</p></td><td><p>1.23</p></td><td><p>1.25</p></td><td><p>1.56</p></td><td><p>1.57</p></td></tr><tr><td><p>Dhrystone/MHz (Ti375 board)</p></td><td><p>1.17</p></td><td><p>1.17</p></td><td><p>1.37</p></td><td><p>1.54</p></td></tr><tr><td><p>fMAX, Titanium Ti375 C529</p></td><td><p>271 MHz</p></td><td><p>278 MHz</p></td><td><p>250 MHz</p></td><td><p>252 MHz</p></td></tr><tr><td><p>fMAX, Topaz Tz170 J484</p></td><td><p>176 MHz</p></td><td><p>170 MHz</p></td><td><p>164 MHz</p></td><td><p>167 MHz</p></td></tr><tr><td><p>fMAX, Trion T120 F324</p></td><td><p>77 MHz</p></td><td><p>77 MHz</p></td><td><p>65 MHz</p></td><td><p>65 MHz</p></td></tr><tr><td><p>Logic/adders, Ti375</p></td><td><p>10,740</p></td><td><p>14,258</p></td><td><p>23,838</p></td><td><p>27,250</p></td></tr><tr><td><p>Memory blocks, Ti375</p></td><td><p>91</p></td><td><p>188</p></td><td><p>128</p></td><td><p>225</p></td></tr><tr><td><p>DSP48 blocks, all three devices</p></td><td><p>17</p></td><td><p>17</p></td><td><p>17</p></td><td><p>17</p></td></tr></tbody></table></div><p><sup>Sources: [1][2][5][8][17]</sup></p><p>All four configurations use 1-way 4 KB L1 caches and a 256-bit AXI4 memory bus; the L2 variants add 64 KB of L2. Basic enables the I, M, A and C extensions; Advanced enables every extension except Zicbom plus all optional features.<sup>[2]</sup> All published figures are single-core. Advanced roughly doubles logic for about a quarter more CoreMark/MHz, and at each configuration's Ti375 fMAX the gain narrows to about 14% (our calculation: 27,250 against 14,258 logic/adders; 252 × 1.57 against 278 × 1.25). Efinix notes that enabling custom instructions, the FPU or the Linux MMU affects fMAX.<sup>[17]</sup></p><h2><br /></h2><p><strong><em>Recommended Reading:</em></strong><em><a href="https://www.wevolver.com/article/risc-v-architecture"> <strong>RISC-V Architecture: A Comprehensive Guide to the Open-Source ISA</strong></a><strong>.</strong> Background on the RV32 and RV64 base ISAs, the standard extensions and the privilege modes that an Sv39 MMU relies on.</em></p><h2>References</h2><ol><li><p><a href="https://www.efinixinc.com/company-pr-efinix-brings-64-bit-riscv-performance-to-embeddded-fpga-designs-with-new-sapphire-rv64-soc.html">Efinix Brings 64-Bit RISC-V Performance to Embedded FPGA Designs With New Sapphire RV64 SoC</a>, Efinix, 28 September 2026. Company press release.</p></li><li><p><a href="https://www.efinixinc.com/docs/riscv-sapphire-rv64-ds-v1.0.pdf">Sapphire RV64 SoC Data Sheet, DS-SAPPHIRE-RV64 v1.0</a>, Efinix, May 2026.</p></li><li><p><a href="https://github.com/SpinalHDL/VexiiRiscv">VexiiRiscv</a>, SpinalHDL, accessed 30 September 2026. Open-source project repository.</p></li><li><p><a href="https://www.businesswire.com/news/home/20240711244170/en/Efinix-Releases-Topaz-Line-of-FPGAs-Delivering-High-Performance-and-Low-Power-to-Mass-Market-Applications">Efinix Releases Topaz Line of FPGAs, Delivering High Performance and Low Power to Mass Market Applications</a>, Business Wire, 11 July 2024. Company press release.</p></li><li><p><a href="https://www.efinixinc.com/docs/trion-overview-v3.3.pdf">Trion FPGA Overview v3.3</a>, Efinix, 2025.</p></li><li><p><a href="https://www.efinixinc.com/docs-html/rv32-sapphire-ds/topics/riscv-saxon-efx-features-sapphire.html">Sapphire RV32 SoC Data Sheet: Features</a>, Efinix, accessed 1 October 2026.</p></li><li><p><a href="https://efinixinc.com/products-linux-riscv.html">Linux + RISC-V Sapphire SoC</a>, Efinix, accessed 1 October 2026.</p></li><li><p><a href="https://github.com/Efinix-Inc/br2-efinix">BR2-Efinix: Buildroot external tree for building Linux for Efinix RISC-V Sapphire SoC</a>, Efinix, branch 2025.02, accessed 1 October 2026. Company board support package.</p></li><li><p><a href="https://www.efinixinc.com/support/ip/riscv-sapphire.php">Sapphire RISC-V SoC</a>, Efinix, accessed 1 October 2026. Product page for the 32-bit soft SoC, with resource and fMAX tables.</p></li><li><p><a href="https://www.businesswire.com/news/home/20240401675642/en/Efinix%E2%80%99s-Titanium-Ti375-Sampling-Unlocking-and-Delivering-Mainstream-Edge-Intelligence-Innovation">Efinix's Titanium Ti375 Sampling; Unlocking and Delivering Mainstream Edge Intelligence Innovation</a>, Business Wire, 1 April 2024. Company press release.</p></li><li><p><a href="https://www.efinixinc.com/docs-html/riscv-sapphire-hpb-ug/topics/riscv-performance-hpb.html">High-Performance Sapphire SoC User Guide: Performance</a>, Efinix, accessed 30 September 2026. Vendor benchmark results.</p></li><li><p><a href="https://www.efinixinc.com/docs-html/rv32-sapphire-hpb-ds/topics/riscv-saxon-efx-features-sapphire-hpb.html">High-Performance Sapphire RV32 SoC Data Sheet: Features</a>, Efinix, accessed 1 October 2026.</p></li><li><p><a href="https://www.efinixinc.com/support/ip/riscv-sapphire-hpb.php">High-Performance Sapphire RV32 SoC</a>, Efinix, accessed 1 October 2026. Product page for the hardened block.</p></li><li><p><a href="https://docs.amd.com/r/en-US/ug1629-microblaze-v-user-guide/Resource-Utilization">MicroBlaze V Processor Reference Guide (UG1629): Resource Utilization</a>, AMD, release 2026.1, 31 July 2026.</p></li><li><p><a href="https://docs.amd.com/r/en-US/ug1629-microblaze-v-user-guide/Memory-Architecture">MicroBlaze V Processor Reference Guide (UG1629): Memory Architecture</a>, AMD, release 2026.1, 31 July 2026.</p></li><li><p><a href="https://www.latticesemi.com/Products/DesignSoftwareAndIP/IntellectualProperty/IPCore/IPCores04/RISC-V-RX-CPU">RISC-V RX CPU IP Core</a>, Lattice Semiconductor, accessed 30 September 2026.</p></li><li><p><a href="https://www.efinixinc.com/docs/riscv-sapphire-rv64-ug-v1.0.pdf">Sapphire RV64 SoC User Guide, UG-SAPPHIRE-RV64 v1.0</a>, Efinix, May 2026.</p></li></ol>

Up to four 64-bit RISC-V cores, a coherent L2 cache and a Linux-capable Sv39 MMU built from FPGA logic.

New 64-bit RISC-V soft SoC for FPGAs with 8 GB DRAM reach

<h2 id="isPasted">Lattice Semiconductor announced the Mach-N2 Family:</h2><p>The Mach-N2 is the newest generation of Lattice's secure-control FPGAs, which handle power sequencing, system management and security. Mach-N2 shares Nexus 2, Lattice's 16 nm FinFET platform, with the general-purpose Certus-N2 family, adding internal flash and run-time security. Its five devices span 40k to 135k LUTs, or 65k to 220k system logic cells.<sup>[1][2][3]</sup></p><p>Lattice says Mach-N2 pairs a hardware root of trust with crypto-agile post-quantum cryptography (PQC) compliant with CNSA 2.0, the NSA's algorithm suite for national security systems. It also claims up to twice the logic density for system control functions and sub-30 ms boot for the 220k-cell device.<sup>[1]</sup> Hardware PQC sits on one device, the 215k-cell MH21D.<sup>[2]</sup></p><h2>Why it matters</h2><p>Lattice pitches Mach-N2 as a first-on, last-off device.<sup>[4]</sup> In NIST's platform firmware resiliency model, SP 800-193, a root of trust protects firmware, detects corruption and restores a known-good image.<sup>[5]</sup> The NSA prioritises firmware signing, whose algorithms are "frequently locked in for the life of a system". CNSA 2.0 lists hash-based LMS and XMSS for firmware signing, ML-DSA-87 for signatures and ML-KEM-1024 for key establishment, and new national security system acquisitions must comply from January 1, 2027.<sup>[6]</sup></p><p>The MH21D adds ML-DSA, LMS, XMSS and stateless hash-based SLH-DSA signatures, plus ML-KEM key exchange, to the classical cryptography all five devices share.<sup>[2]</sup> Lattice's previous PQC-capable parts belong to its MachXO5-NX secure-control family, whose TDQ devices launched in October 2025 on 28 nm FD-SOI and now reach 64k logic cells with PCIe Gen2 x1.<sup>[7][8]</sup> The MH21D's 132k LUTs are about 2.5 times the largest TDQ device's roughly 53k (author's calculation, 64k cells ÷ 1.2 cells per LUT), and its hard PCIe controller runs Gen4 x4.<sup>[2]</sup></p><p>The MH21D comes only in an 18 × 18 mm CBG484 package with 236 user I/O and in the two slower speed grades; it needs customer keys and policy provisioned before first use. Mach-N2 tops out at 248 user I/O, 92 of them 3.3 V-capable, where the largest MachXO5-NX packages reach 360 or more, over 300 of them 3.3 V-capable. Mach-N2 also drops the 12-bit SAR ADCs that MachXO5-NX provides for system monitoring.<sup>[2][8][9]</sup></p><p>Some competing FPGAs already offer post-quantum boot. AMD's cost-optimised Spartan UltraScale+ SU200P targets board management and platform root of trust with up to 572 I/O and up to eight transceivers. The SU200P authenticates boot images with hash-based HSS/LMS signatures or ECDSA P-384 and receives its configuration from external memory or a host at every power-up.<sup>[10][11][12]</sup> Altera said in September that PQC-enabled Agilex 3 and Agilex 5 FPGAs are shipping.<sup>[13]</sup> Mach-N2 instead boots from internal flash; Lattice says configuration data is never exposed outside the device while loading.<sup>[14]</sup></p><h2>Technical specifications</h2><h3>Mach-N2 devices</h3><div><table><thead><tr><th>Spec</th><th>MH06</th><th>MH10</th><th>MH16</th><th>MH20</th><th>MH21D</th></tr></thead><tbody><tr><td>System logic cells</td><td>65k</td><td>100k</td><td>160k</td><td>220k</td><td>215k</td></tr><tr><td>LUTs</td><td>40k</td><td>61k</td><td>98k</td><td>135k</td><td>132k</td></tr><tr><td>Block RAM (36 kbit blocks)</td><td>114</td><td>153</td><td>228</td><td>306</td><td>289</td></tr><tr><td>18 × 18 multipliers</td><td>120</td><td>240</td><td>360</td><td>520</td><td>520</td></tr><tr><td>Hardware PQC and crypto agility</td><td>No</td><td>No</td><td>No</td><td>No</td><td>Yes</td></tr><tr><td>Packages (0.8 mm pitch)</td><td>CBG256 (14 × 14 mm), CBG484 (18 × 18 mm)</td><td>CBG256, CBG484</td><td>CBG484</td><td>CBG484</td><td>CBG484</td></tr><tr><td>User I/O, total (3.3 V-capable wide-range / high-performance)</td><td>141 (39 / 102) in CBG256; 196 (92 / 104) in CBG484</td><td>141 (39 / 102) in CBG256; 196 (92 / 104) in CBG484</td><td>248 (92 / 156)</td><td>248 (92 / 156)</td><td>236 (83 / 153)</td></tr><tr><td>Transceiver lanes</td><td>2 in CBG256; 4 in CBG484</td><td>2 in CBG256; 4 in CBG484</td><td>4</td><td>4</td><td>4</td></tr><tr><td>Speed grades</td><td>1 to 3</td><td>1 to 3</td><td>1 to 3</td><td>1 to 3</td><td>1 and 2</td></tr><tr><td>User flash memory (UFM)</td><td>not stated</td><td>not stated</td><td>105,472 kbit</td><td>105,472 kbit</td><td>not stated</td></tr><tr><td>Internal flash, total</td><td>not stated</td><td>not stated</td><td>not stated</td><td>256 Mbit</td><td>not stated</td></tr><tr><td>Configuration time</td><td>not stated</td><td>not stated</td><td>not stated</td><td>under 30 ms (Lattice claim)</td><td>not stated</td></tr><tr><td>Flash data retention at 100 °C junction</td><td>20 years</td><td>20 years</td><td>20 years</td><td>20 years</td><td>not stated</td></tr><tr><td>Flash programming cycles within retention spec (write/erase maximum)</td><td>10,000 (100,000)</td><td>10,000 (100,000)</td><td>10,000 (100,000)</td><td>10,000 (100,000)</td><td>not stated</td></tr></tbody></table></div><h3>Shared by all five Mach-N2 devices</h3><div><table><thead><tr><th>Spec</th><th>Value</th></tr></thead><tbody><tr><td>Platform and process</td><td>Lattice Nexus 2, TSMC 16 nm FinFET</td></tr><tr><td>Core supply</td><td>0.82 V</td></tr><tr><td>Transceivers</td><td>up to 16 Gb/s per lane</td></tr><tr><td>PCIe</td><td>hard Gen4 (16 GT/s) controller, up to x4, up to eight physical functions</td></tr><tr><td>Ethernet</td><td>10GbE, with PMA and PCS in hardware and the MAC in fabric</td></tr><tr><td>External memory</td><td>DDR4 and LPDDR4 up to 2400 Mb/s</td></tr><tr><td>Configuration</td><td>boots from internal flash (self-download mode); images programmed over JTAG or target SPI; no boot from external SPI flash</td></tr><tr><td>Image fallback</td><td>up to three stored images: primary, secondary and golden (Lattice); falls back on a failed authentication or a bitstream revision below the set minimum</td></tr><tr><td>Bitstream protection</td><td>AES-256-GCM encryption; ECDSA (up to 521-bit) or RSA (up to 4096-bit) authentication</td></tr><tr><td>Run-time cryptography</td><td>AES-256 engines at up to 2.5 Gb/s and 10 Gb/s; SHA-2, SHA-3 and HMAC up to 512 bits; ECDSA, ECDH and ECIES up to 521 bits; Ed25519; RSA 2048 to 4096; TRNG</td></tr><tr><td>Device identity</td><td>physically unclonable function (PUF), 256 bits of entropy, stable for more than 20 years; Lattice lists DICE and SPDM attestation on the PUF-derived identity</td></tr><tr><td>Anti-tamper</td><td>voltage and temperature monitor, plus user-triggered responses ranging from zeroising RAM and stored secrets to permanently disabling the device</td></tr><tr><td>Temperature grades</td><td>commercial 0 to 85 °C; industrial -40 to 100 °C</td></tr><tr><td>Power consumption</td><td>not stated</td></tr></tbody></table></div><h3>MH21D root-of-trust device: differences from the other four</h3><div><table><thead><tr><th>Spec</th><th>Value</th></tr></thead><tbody><tr><td>Post-quantum signatures</td><td>ML-DSA, LMS, XMSS, SLH-DSA</td></tr><tr><td>Post-quantum key exchange</td><td>ML-KEM</td></tr><tr><td>Other additions</td><td>Ed448; SHAKE128 and SHAKE256; crypto agility with field-updatable algorithms (Lattice)</td></tr><tr><td>ML-DSA and ML-KEM parameter sets</td><td>not stated (CNSA 2.0 requires ML-DSA-87 and ML-KEM-1024)</td></tr><tr><td>Secret storage</td><td>one-time-programmable memory; the battery-backed RAM option is not available</td></tr><tr><td>Provisioning</td><td>customer policy and key files plus an authenticated image, loaded over JTAG or target SPI before the first reboot</td></tr></tbody></table></div><p><sup>Sources: [1][2][3][4][14][15][16]</sup></p><p>All Mach-N2 specifications are preliminary. Cell counts do not compare across generations: Nexus 2 system logic cells run about 1.63 per LUT against 1.2 for MachXO5-NX logic cells, so the 220k-cell MH20 has about 1.7 times the LUTs of the largest MachXO5-NX (our calculation).<sup>[2][9]</sup> Lattice quotes a boot time under 30 ms for the MH20, whose uncompressed bitstreams are 44 Mbit to 64.1 Mbit.<sup>[1][14]</sup> For CNSA 2.0 designs, the MH21D's parameter sets are a gating item; boot time and power only set budgets. Lattice's evaluation board carries an MH20, which lacks the PQC engines.<sup>[17]</sup></p><h2><br /></h2><p><strong><em>Recommended reading:</em></strong><em><a href="https://www.wevolver.com/article/quantum-resistant-security-on-altera-fpga"> <strong>Post-quantum secure boot reaches low-cost and mid-range FPGAs</strong></a><strong>.</strong> How Altera placed PQC bitstream authentication in the Agilex 3 and Agilex 5 Secure Device Manager, and where other vendors put it in the boot chain.</em></p><h2>References</h2><ol><li><a href="https://www.businesswire.com/news/home/20260916542312/en/Lattice-Expands-Secure-Control-FPGA-Leadership-with-New-Lattice-Mach-N2-Family">Lattice Expands Secure Control FPGA Leadership with New Lattice Mach-N2 Family</a>, Lattice Semiconductor via Business Wire, September 16, 2026.</li><li><a href="https://www.latticesemi.com/view_document?document_id=54437">Lattice Nexus 2 Platform: Overview Data Sheet (FPGA-DS-02122, v0.80)</a>, Lattice Semiconductor, September 2026. Preliminary vendor datasheet.</li><li><a href="https://www.businesswire.com/news/home/20241210483055/en/Lattice-Advances-Low-Power-FPGA-Leadership-with-New-Small-and-Mid-range-FPGA-Offerings/">Lattice Advances Low Power FPGA Leadership with New Small and Mid-range FPGA Offerings</a>, Lattice Semiconductor via Business Wire, December 10, 2024.</li><li><a href="https://www.latticesemi.com/Products/FPGAandCPLD/Mach-N2">Mach-N2</a>, Lattice Semiconductor product page, accessed September 30, 2026.</li><li><a href="https://nvlpubs.nist.gov/nistpubs/SpecialPublications/NIST.SP.800-193.pdf">Platform Firmware Resiliency Guidelines (NIST SP 800-193)</a>, National Institute of Standards and Technology, May 2018.</li><li><a href="https://media.defense.gov/2022/Sep/07/2003071836/-1/-1/0/CSI_CNSA_2.0_FAQ_.PDF">The Commercial National Security Algorithm Suite 2.0 and Quantum Computing FAQ</a>, National Security Agency, December 2024. Cybersecurity Information Sheet, version 2.1.</li><li><a href="https://www.businesswire.com/news/home/20251013522544/en/Lattice-Launches-Industry-First-PQC-Ready-FPGA-Family-MachXO5-NX-TDQ">Lattice Launches Industry-First PQC-Ready FPGA Family: MachXO5-NX TDQ</a>, Lattice Semiconductor via Business Wire, October 13, 2025.</li><li><a href="https://www.latticesemi.com/view_document?document_id=54310">MachXO5-NX Family Root-of-Trust Devices Data Sheet (FPGA-DS-02120, v1.5)</a>, Lattice Semiconductor, August 2026. Vendor datasheet.</li><li><a href="https://www.latticesemi.com/view_document?document_id=53488">MachXO5-NX Family Data Sheet (FPGA-DS-02102, v2.3)</a>, Lattice Semiconductor, July 2026. Vendor datasheet.</li><li><a href="https://www.amd.com/en/blogs/2026/amd-spartan-fpga-grows-up-bigger-smarter-scalable-more-secure.html">AMD Spartan FPGA Grows Up: Bigger, Smarter, Scalable, More Secure</a>, AMD, June 15, 2026. Vendor blog.</li><li><a href="https://docs.amd.com/r/en-US/ug1283-bootgen-user-guide/Spartan-UltraScale-Authentication-Certificate">Spartan UltraScale+ Authentication Certificate (Bootgen User Guide, UG1283)</a>, AMD, June 2026. Vendor user guide.</li><li><a href="https://www.amd.com/content/dam/amd/en/documents/products/adaptive-socs-and-fpgas/vivado/configuration-flow-for-spartan-ultrascale-plus.pdf">Configuration Flow for AMD Spartan UltraScale+ Devices</a>, AMD, 2025. Vendor presentation.</li><li><a href="https://www.altera.com/newsroom/post-quantum-security">Altera Adds Post-Quantum Security to Agilex 3 and Agilex 5 FPGAs</a>, Altera press release, September 8, 2026.</li><li><a href="https://www.latticesemi.com/view_document?document_id=54443">Lattice Nexus 2 sysCONFIG User Guide (FPGA-TN-02370, v0.82)</a>, Lattice Semiconductor, September 2026. Preliminary vendor technical note.</li><li><a href="https://www.latticesemi.com/view_document?document_id=54436">Lattice Nexus 2 Platform: Specifications Data Sheet (FPGA-DS-02121, v0.80)</a>, Lattice Semiconductor, September 2026. Preliminary vendor datasheet.</li><li><a href="https://www.latticesemi.com/view_document?document_id=54471">Lattice Nexus 2 Multi-Boot User Guide (FPGA-TN-02385, v0.81)</a>, Lattice Semiconductor, September 2026. Preliminary vendor technical note.</li><li><a href="https://www.latticesemi.com/view_document?document_id=55346">Mach-N2 Evaluation Board (FPGA-EB-02078, v0.81)</a>, Lattice Semiconductor, September 2026. Vendor board guide.</li></ol>

Lattice's Mach-N2 FPGAs pair internal-flash boot with PCIe Gen4 and 16 Gb/s transceivers for compute and communications infrastructure.

Secure-control FPGA puts post-quantum root of trust on 215k-logic-cell device

<h2 id="isPasted">What is the announcement</h2><p>Altera announced that post-quantum cryptography support now covers its Agilex 3 and Agilex 5 FPGAs, the company's low-cost and mid-range families. PQC-enabled secure boot runs in the Secure Device Manager, the on-chip block that authenticates the configuration bitstream before the fabric loads, and which also provides bitstream encryption, physical anti-tamper support, key management, physically unclonable function keys and platform attestation. </p><p>Version 26.1.1 of Quartus Prime Pro Edition, Altera's FPGA design software, supplies the supporting flow, and PQC-enabled devices are shipping.<sup>[1]</sup></p><h2>Why does it matter</h2><p>Where the post-quantum step sits matters a lot. On Agilex it is in the Secure Device Manager, which runs first. The nearest alternatives place it higher up the chain. </p><p>The Microchip PolarFire SoC system controller authenticates its boot image using elliptic curve cryptography.<sup>[6]</sup> The AMD Zynq UltraScale+ immutable BootROM authenticates the first-stage bootloader with RSA-4096.<sup>[7]</sup> However, wolfSSL, which supplies such a bootloader, states plainly that post-quantum verification through a bootloader layered above a classical first stage this does not make the BootROM quantum-safe.<sup>[7]</sup> </p><p>PQC secure boot is not new to the family. Altera introduced it in September 2025 on Agilex 5 D-Series devices, the higher-density tier of that mid-range family.<sup>[2]</sup> <strong>What arrives now is coverage of Agilex 3 and the wider Agilex 5 line, plus a supporting design-software flow. That matters most at the lower-cost end, where security features usually appear last.</strong></p><p>Which algorithm it uses decides whether it can satisfy a compliance mandate. CNSA 2.0 requires LMS or XMSS, the stateful hash-based schemes standardised in NIST SP 800-208, for firmware and software signing, and ML-DSA-87 under FIPS 204 for general-purpose signatures.<sup>[4][5]</sup>  However, the algorithm and parameter set used are not named in the announcement or in the public Agilex configuration and security documentation.<sup>[1][3]</sup> </p><h2>Technical specifications</h2><table><tbody><tr><td><strong>Item</strong></td><td><strong>Value</strong></td><td><strong>Source</strong></td></tr><tr><td>Devices</td><td>Agilex 3 and Agilex 5 FPGAs and SoCs</td><td>Altera<sup>[1]</sup></td></tr><tr><td>Feature</td><td>PQC-enabled secure boot in the Secure Device Manager</td><td>Altera<sup>[1]</sup></td></tr><tr><td>Other SDM security features</td><td>Bitstream encryption, physical anti-tamper, key management, PUF keys, embedded cryptographic cores, platform attestation</td><td>Altera<sup>[1]</sup></td></tr><tr><td>Tool support</td><td>Quartus Prime Pro Edition 26.1.1</td><td>Altera<sup>[1]</sup></td></tr><tr><td>Availability</td><td>Shipping</td><td>Altera<sup>[1]</sup></td></tr><tr><td>First appearance of PQC secure boot in the family</td><td>Agilex 5 D-Series, September 2025, with Quartus Prime 25.3</td><td>Altera<sup>[2]</sup></td></tr><tr><td>Classical bitstream authentication scheme</td><td>First-level signature chain (.qky), root key SHA-256 or SHA-384 hash stored in eFuses</td><td>Quartus Prime Pro Programmer User Guide<sup>[3]</sup></td></tr><tr><td>PQC algorithm and parameter set</td><td>Not stated</td><td>-</td></tr><tr><td>Hybrid classical plus PQC, or PQC only</td><td>Not stated</td><td>-</td></tr></tbody></table><p><sup>Source: [1][2][3]</sup></p><p id="isPasted">Secure boot authenticates the configuration bitstream. It does not by itself protect data in transit or at rest, which still needs key establishment, and the new capability covers signature verification only. Post-quantum signatures are substantially larger than ECDSA signatures, so configuration time and flash budget are worth measuring on a real bitstream before a board layout is committed. </p><p><strong><em>Recommended reading: </em></strong><a href="https://www.wevolver.com/article/cpld-vs-fpga-a-comprehensive-technical-analysis-and-implementation-guide"><em>On choosing between CPLDs and FPGAs</em></a><em>; where Agilex 3 and Agilex 5 sit in the device landscape.</em></p><h2>References</h2><ol><li>Altera Corporation, "Altera Adds Post-Quantum Security to Agilex 3 and Agilex 5 FPGAs", Business Wire, 8 September 2026. <a href="https://www.businesswire.com/news/home/20260908566243/en/Altera-Adds-Post-Quantum-Security-to-Agilex-3-and-Agilex-5-FPGAs" target="_blank" rel="noopener noreferrer">(link)</a></li><li>Altera Corporation, "Altera Expands Agilex FPGA Portfolio and Streamlines Developer Experience", Business Wire, 30 September 2025. <a href="https://www.businesswire.com/news/home/20250930261258/en" target="_blank" rel="noopener noreferrer">(link)</a></li><li>Quartus Prime Pro Edition User Guide: Programmer, "Enabling Bitstream Authentication". <a href="https://intel.com/content/www/us/en/docs/programmable/683039/24-1/enabling-bitstream-authentication-programming.html" target="_blank" rel="noopener noreferrer">(link)</a></li><li>postquantum.com, "NSA Updates CNSA 2.0 After NIST Finalizes PQC Standards", on the CNSA 2.0 FAQ v2.1. <a href="https://postquantum.com/security-pqc/nsa-cnsa-2-0-faq-v2-1-update/" target="_blank" rel="noopener noreferrer">(link)</a></li><li>QCecuring, "CNSA 2.0 Compliance Guide", June 2026. <a href="https://www.qcecuring.com/blog/cnsa-2-0-compliance-guide-2026" target="_blank" rel="noopener noreferrer">(link)</a></li><li>Microchip Technology, "Boot With Trust: How PolarFire SoC FPGAs Provide Secure Startup". <a href="https://www.microchip.com/en-us/about/media-center/blog/2025/boot-with-trust-polarfire-soc-fpgas-secure-startup">(link)</a></li><li>wolfSSL, "wolfBoot for CNSA 2.0 Secure Boot on Zynq UltraScale+ MPSoC", June 2026. <a href="https://www.wolfssl.com/wolfboot-for-cnsa-2-0-secure-boot-on-zynq-ultrascale-mpsoc/" target="_blank" rel="noopener noreferrer">(link)</a></li><li>wolfSSL, "Announcing wolfBoot Support for Microchip PolarFire SoC", December 2025. <a href="https://www.wolfssl.com/announcing-wolfboot-support-for-microchip-polarfire-soc/">(link)</a></li><li>iWave Global, "Post-Quantum Cryptography on Agilex 5 System on Module", with Xiphera xQlave ML-KEM and ML-DSA cores. <a href="https://iwave-global.com/articles/post-quantum-cryptography-on-agilex-5-system-on-module/" target="_blank" rel="noopener noreferrer">(link)</a></li></ol>

Altera has extended quantum-resistant bitstream authentication to its mid-range Agilex 5 FPGAs and the low-cost Agilex 3 family, running in the on-chip block that loads the device. Shipping now.

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Post-quantum secure boot reaches low-cost and mid-range FPGAs