AI chip design RTL generation agent delivers area and power reduction

What was announced

Cadence Design Systems announced the RTL Generation Agent on 22 September 2026 as an addition to ChipStack AI Super Agent, the company's agentic software for front-end digital design and verification. The agent generates register-transfer level (RTL) code from a natural-language specification, analyzes and refines it against power, performance and area (PPA) targets, and can update existing RTL to meet new architectural, functional or PPA requirements.^[1]

Cadence says that in early evaluations the RTL Generation Agent delivered on average 24% less area and 18% less power than "pure foundation model code generation", with 100% functionally accurate RTL. Honda R&D is evaluating the agent on automotive SoCs. Early access for select customers is expected in the fourth quarter of 2026.^[1]

Why it matters

Language models have no intrinsic way to quantify PPA from code, the authors of VeriOpt, a 2025 academic framework, noted.^[2] Cadence's agent is built to close that gap with its own tools.

A Cadence video describes two reinforcement-learning loops: the first uses a language model to write C++ and optimizes the architecture, the second optimizes the RTL with Cadence's synthesis and analysis engines, and each repeats until a PPA check passes. The video's demo shows a route from specification to C++ to RTL: the C++ is written for Stratus, Cadence's high-level synthesis tool, and the output is synthesizable Verilog.^[3][4]

Cadence's video shows the benchmark behind its claims of 24% less area and 18% less power. Three general-purpose language models each generated nine designs two ways: writing the RTL directly, which is Cadence's baseline, and working through the RTL Generation Agent.^[3]

Written directly, the RTL still failed simulation after 20 attempts in 8 of 27 runs, including all three models on the attention and softmax_fp16 designs. Through the agent, all 27 runs passed simulation and met timing.^[3]

Both claims are taken from the unweighted average of the 19 runs that passed both ways. The spread is wide: the agent's RTL ranged from 47% smaller to 58% larger in area than the directly written RTL.^[3]

The route has a commercial precedent. By July 2025 Rise Design Automation, a start-up, was offering high-level synthesis tools in which a language model helps write the C++, SystemC or SystemVerilog model that is synthesized into RTL.^[5] Rise's current platform feeds PPA results from its own toolchain back to the model; Rise says they correlate to within 10% of production RTL synthesis.^[6] Cadence's agent applies the idea with its own synthesis and power-analysis engines and adds benchmark data.

Siemens and Synopsys announced natural-language RTL agents earlier in 2026, described in productivity terms. Siemens's RTL Code Agent, part of its Questa One verification software, writes synthesizable RTL while checking for coding violations, and its Fuse EDA AI Agent supports automated RTL coding with Catapult, Siemens's high-level synthesis software.^[7][8][9] Synopsys says its AgentEngineer workflow, which generates RTL from natural-language and formal specifications, doubles productivity for customers, with up to 5x in select cases.^[10] ChipStack AI Super Agent itself listed design coding at its February 2026 launch.^[11]

Technical specifications

RTL Generation Agent (Cadence ChipStack AI Super Agent)

Cadence's benchmark for the RTL Generation Agent

^{Sources: [1][3][4][12]}

The two approaches are not compared at equal throughput: by our count the agent's RTL needs fewer cycles per output in 14 of the 19 comparable runs and more in 3. On layer_norm, claude-sonnet-4-6's direct RTL is smaller (area 3,079 against 4,877, units unlabeled) but needs 200 cycles per output against 100.^[3] EvolVE, a January 2026 academic framework, compares at identical clock frequency and against human-written reference designs, reporting a 17% geometric-mean reduction in PPA product at TSMC 180 nm.^[13] Cadence's table has no human-written reference, which blocks a comparison with existing RTL; the unlabeled units and unstated library limit how far the averages generalize. Tom's Hardware reported on 30 September 2026 that agent platforms from Cadence, Synopsys and Siemens were all still in early access or evaluation.^[14]

Recommended reading

ASIC Design: A Step-by-Step Guide from Specification to Silicon. Shows where RTL coding, verification, synthesis and timing analysis sit in the flow from specification to tape-out.

RTL Design: A Comprehensive Guide to Understanding and Implementing Register-Transfer Level Design. Explains what RTL describes and how the RTL design process runs, including where high-level synthesis fits.

References

1. Cadence Expands ChipStack AI Super Agent with a New Agent for RTL Generation and Early PPA Optimization, Cadence Design Systems, 22 September 2026. Press release.
2. VeriOpt: PPA-Aware High-Quality Verilog Generation via Multi-Role LLMs, Tasnia et al., arXiv, 20 July 2025. Research paper accepted for ICCAD 2025.
3. RTL Generation Agent: AI-Powered RTL Generation for PPA-Optimized Chip Design, Cadence Design Systems, last modified 16 September 2026. Company video; the method, demo and benchmark details are taken from its slides, terminal demo and narration.
4. Stratus High-Level Synthesis, Cadence Design Systems, accessed 5 October 2026. Product page.
5. EDA Startups At DAC 2025, Semiconductor Engineering, 9 July 2025. Trade-press round-up of new exhibitors.
6. Rise Agentic AI: Rise AI IPCreate Platform, Rise Design Automation, published 1 April 2026, modified 21 July 2026. Vendor product page.
7. Siemens accelerates integrated circuit design and verification with agentic AI in Questa One, Siemens Industry Software, 27 February 2026. Press release.
8. Siemens launches Fuse EDA AI Agent for automation across semiconductor, 3D IC and PCB system workflows, Siemens, 16 March 2026. Press release.
9. Siemens advances self-verifying agentic AI workflows for semiconductor and PCB design, Siemens, 26 July 2026. Press release.
10. Synopsys Outlines Vision for Engineering the Future, Synopsys, 11 March 2026. Press release.
11. Cadence Unleashes ChipStack AI Super Agent, Pioneering a New Frontier in Chip Design and Verification, Cadence Design Systems, 10 February 2026. Press release.
12. ChipStack AI Super Agent, Cadence Design Systems, accessed 5 October 2026. Product page.
13. EvolVE: Evolutionary Search for LLM-based Verilog Generation and Optimization, Hsin et al., arXiv, 26 January 2026. Research preprint.
14. The state of agentic AI in chip design tools in 2026: Cadence, Synopsys, and Siemens all pitch autonomous engineers, Tom's Hardware, 30 September 2026. Independent feature.