Dual-rail qubit emulator lets quantum programs act on detected errors
D-Wave, supplier of quantum computers, has opened a limited cloud beta of a 21-qubit emulator for gate-model hardware it has yet to release.
02 Oct, 2026. 4 minutes read
D-Wave gate-model quantum chip
What was announced
D-Wave Quantum launched a beta program on 1 October 2026 for its gate-model quantum computing simulator, a classical emulator announced in June 2026 and built around its dual-rail superconducting qubit technology. Select customers get access through D-Wave's Leap quantum cloud service and Ocean software development kit ahead of general availability. Named participants are the bank BBVA, FirstQFM (which builds foundation models for quantum computing), Florida Atlantic University and the Jülich Supercomputing Centre. D-Wave says the dual-rail design uses error detection to deliver error correction with "significantly lower hardware overhead as systems scale." The technology comes from Quantum Circuits Inc., a dual-rail qubit developer co-founded by Yale professor Rob Schoelkopf, which D-Wave acquired in January 2026.[1][2][3][4]
Why it matters
A dual-rail cavity qubit stores one microwave photon shared between two superconducting cavities. Photon loss, the dominant error, leaves both cavities empty: a state outside the code space, detectable without disturbing the logical state. Errors at known locations are erasures, and a code of given distance corrects roughly twice as many of them as errors at unknown locations.[5][6]
The simulator exposes this to programmers. In QCDL, D-Wave's Python-embedded circuit language, a measurement returns 0, 1 or *, where * marks a qubit detected outside the code space. A non-destructive mced() instruction checks for erasure mid-circuit, conditional blocks can branch on the result, and jobs can post-select erasure-free shots. The simulator's noisy mode applies Pauli errors, leakage and seepage (return into the code space) after gates and idle periods.[7][8]
D-Wave ties the simulator to a controlled-Z (CZ) gate its researchers reported in Nature in August 2026.[1][9] On a two-qubit device, the roughly 500 ns gate flagged an erasure in about 0.5% of operations; with erasures discarded, randomized benchmarking gave 0.108% residual error per gate. A surface-code simulation with that error structure gave Λ, the factor by which logical error falls when code distance rises by two, of about 27, against about 14 for 0.1% depolarizing noise. The authors note that model counted only CZ errors and perfect erasure checks; adding single-qubit gate, measurement and idle errors lowers Λ.[9]
Oxford Quantum Circuits, also a dual-rail qubit developer, released Erado in March 2026: an open-source Qiskit-based library whose 16-qubit backend models erasure noise only and returns no per-shot erasure flags.[10][11][12][13] Quantum Circuits announced an error-aware simulator with real-time control flow for select customers in June 2024.[14] D-Wave's beta reports erasures per shot and mid-circuit, and models Pauli errors too. Its documented targets are 17 and 21 qubits; D-Wave's roadmap lists a 17-physical-qubit system for 2026.[4][8]
The beta suits developers testing erasure-aware logic on one hardware model, not large circuits or calibrated fidelity estimates.
Technical Specifications
D-Wave gate-model simulator (Leap Beta, per Ocean SDK documentation, October 2026)
| Spec | Value |
|---|---|
| Emulated hardware | Dual-rail superconducting cavity qubits |
| Maximum circuit size | 21 qubits |
| Simulator targets | DRsim_17qubits, DRsim_21qubits |
| Simulation method | Monte Carlo; runtime O(s·g·2ⁿ) for s shots, g gates, n qubits |
| Ideal mode | State vector, no noise; all Qiskit gates; mced() always returns 0 |
| Noisy mode | Pauli errors, leakage and seepage applied randomly after gates and idles; basis gates only; same scaling, slower |
| Error injection | leak and seep instructions (noisy mode) |
| Basis gates (noisy mode) | sx, x, rz, cz |
| Measurement outcomes | 0, 1, * (erased) |
| Mid-circuit error detection | mced(), non-destructive |
| Classical control | If, While, DoWhile, For |
| Post-selection | Repeat until the requested number of erasure-free shots is collected |
| Shots per job | 1 to 1,000,000 (default 1,000) |
| Job time limit | 1 to 2,700 s |
| Programming interfaces | QCDL (Python), Ocean SDK; Qiskit integration (D-Wave fact sheet) |
| Access | Leap cloud service, invited beta |
| Noise-model error rates | Not stated |
| Pricing | On request (Starter and Premium bundles announced June 2026) |
| General availability date | Not stated |
Dual-rail CZ gate, two-qubit device (Nature, 5 August 2026)
| Spec | Value |
|---|---|
| Gate duration | About 500 ns |
| Detected erasure per CZ gate | 0.53% (repeated Bell-state tomography); 0.69% (interleaved randomized benchmarking) |
| Residual error per CZ gate, erasures discarded | 0.108% (interleaved randomized benchmarking) |
| Single-qubit gates | About 0.1% erasure; about 0.01% residual error |
| Simulated surface-code Λ | About 27 (CZ errors only, perfect erasure checks); about 14 for 0.1% depolarizing noise |
Sources: [2][8][9][15][16]
Everything in the first table describes a classical emulation whose runtime doubles with each added qubit. D-Wave's documentation and fact sheet do not give the error rates or qubit connectivity behind the noise model. That does not block prototyping control flow around erasure flags, but it does limit what noisy-mode results say about hardware fidelity. The gate figures come from a two-qubit device, and Aqumen Seeker, the dual-rail processor Quantum Circuits launched in November 2024, has 8 qubits. Neither is hardware at the 17- or 21-qubit scale the simulator emulates.[17]
Recommended reading: A Full Quantum Error Correction Stack for 408 Logical Qubits Ran on a Standard CPU. IonQ's real-time decoder covers the classical side of acting on error information while a computation runs.
References
- D-Wave Launches Gate-Model Simulator Beta Program, Advancing Error-Aware Programming Capabilities, D-Wave Quantum via Business Wire, 1 October 2026
- D-Wave to Launch Gate-Model Quantum Simulator with Dual-Rail Error Detection, HPCwire, 18 June 2026 (reprint of D-Wave's press release)
- D-Wave Announces Agreement to Acquire Quantum Circuits Inc., D-Wave Quantum, 7 January 2026
- D-Wave Reports Second Quarter 2026 Results, D-Wave Quantum, 6 August 2026 (includes the gate-model roadmap)
- Dual-rail encoding with superconducting cavities, Teoh et al., PNAS, 2023 (peer-reviewed; Yale research that preceded the Quantum Circuits hardware)
- Erasure qubits: Overcoming the T1 limit in superconducting circuits, Kubica et al., arXiv, 2022 (AWS Center for Quantum Computing, Caltech and Hebrew University of Jerusalem)
- dwave-gate, D-Wave Ocean SDK documentation, version 0.6.0, accessed October 2026
- Using dwave-gate, D-Wave Ocean SDK documentation, version 0.6.0, accessed October 2026 (simulator modes, parameters and properties)
- An entangling gate for dual-rail erasure qubits, Mehta et al., Nature, 5 August 2026 (peer-reviewed, open access; authors at D-Wave and Yale)
- OQC Announces Research on Path to Commercially-Viable Quantum Computers, Oxford Quantum Circuits, 19 June 2025 (company press release)
- erado, Python Package Index, release history (version 1.0.0 released 11 March 2026)
- Making Quantum Errors Visible: A New Approach to Reliable Quantum Computing, Oxford Quantum Circuits, 1 July 2026 (company blog)
- Erado Basic Simulator, OQC QCaaS SDK documentation, accessed October 2026
- Quantum Circuits Developing Quantum Software Platform With Built-in Qubit Error Detection, The Quantum Insider, 18 June 2024 (reprint of a Quantum Circuits press release)
- QCDL API reference, D-Wave Ocean SDK documentation, version 0.6.0, accessed October 2026
- D-Wave's Gate-Model Quantum Simulator, D-Wave product fact sheet, 2026
- Quantum Circuits Accelerates Momentum Toward Commercial Quantum Computing With New Aqumen Seeker Quantum Processing Unit, Quantum Circuits, 19 November 2024 (company press release)