A Full Quantum Error Correction Stack for 408 Logical Qubits Ran on a Standard CPU

IonQ announced an end-to-end real-time quantum error correction decoder that runs on one off-the-shelf processor, which the company calls an industry first. In benchmark circuits the decoder covered up to 408 logical qubits across 88 memory blocks and magic state factories, the blocks that supply the non-Clifford resources a universal computation needs, executing more than 31.5 million quantum operations. IonQ reports it added "as little as 0.02%" stretch, its term for the extra time a computation spends waiting on decoding.^[1] The supporting paper by Min Ye, Andrii Maksymov and Nicolas Delfosse gives the range behind that figure: stretch stayed below 0.3% at a two-qubit gate error rate of 1×10⁻⁴, and below 12% at 5×10⁻⁴.^[2]

Why it matters

A decoder that falls behind the syndrome stream gathers work faster than it clears it. A 2023 review in Nano Futures calls this the backlog problem, crediting B. M. Terhal's 2015 analysis, and puts the resulting slowdown at exponential. The same review sets the throughput target at roughly 1 µs per cycle for superconducting transmon qubits, about 1 ms for silicon spin qubits, and beyond 100 ms for ion traps.^[3]

Timing budget is why a general-purpose processor suffices here:

IonQ's simulation assumes a syndrome extraction cycle of 1 ms to 5 ms, which the paper attributes to what small trapped-ion devices have achieved.^[2] For comparison, Riverlane, which builds real-time error correction systems, reported 16.32 µs mean system latency in April 2026 decoding Google's 2024 Willow processor data at distance 5, against the 63 µs Google reported. At microsecond clocks, decoding tends to move into custom hardware: Riverlane credits part of its margin to a Local Clustering Decoder on FPGAs, against what it describes as Google's software decoder.^[4] A millisecond clock leaves more room for software, though IonQ's 1 ms assumption is still far tighter than the 100 ms that review expected of ion traps.

Noise binds this result more than qubit count does. Stretch rose by a factor of roughly 35 to 60 across the three workloads when the simulated two-qubit error rate moved from 1×10⁻⁴ to 5×10⁻⁴ (author's calculation from the paper's figures). Tail latency is the mechanism: on the 408-qubit workload at 5×10⁻⁴, the error decoder's worst window took 41.86 ms against the 15 ms available in three committed 5 ms cycles.^[2] IonQ's Walking Cat architecture, its trapped-ion fault-tolerance blueprint from April 2026, already described a streaming decoder fast enough for online decoding.^[5] What is new is the complete pipeline measured together, detector error model generation and magic state factories included.

Technical Specs: Benchmark workloads and decoding overhead

^{Source: [2]}

Every performance figure in the table comes from simulation: syndromes were generated by a circuit-level noise model, and the paper reports no run against physical hardware. It also substitutes a stabilizer state for the physical magic state during initial preparation, a simplification the authors say suits a decoder-load benchmark, leaving output fidelity untested. The headline 0.02% belongs to the workload with a 5 ms cycle, five times the budget of the 102-qubit runs, so its clock flatters the result. The announcement's 31.5 million figure matches that workload's syndrome cycle count exactly; the paper lists 1,318,310 logical measurements and 555,130 T gates. For anyone sizing a control stack, the worst-case window matters more than the mean: backlog clears only by postponing the next cat-based measurement, so tail latency sets the logical clock.

Recommended Reading: The Quantum Web: Interconnecting Quantum Processors for Larger-Scale Machines. How linking processors raises qubit counts and system-wide fault tolerance, the scaling route this decoding work is meant to support.

References

1. IonQ Demonstrates Industry's First End-to-End Real-Time Quantum Error Decoder, IonQ press release, 22 September 2026.
2. Real-time decoder for a MegaQuOp quantum computer using a single CPU, Min Ye, Andrii Maksymov, Nicolas Delfosse, arXiv preprint (not peer reviewed), 25 August 2026, revised 3 September 2026.
3. Real-Time Decoding for Fault-Tolerant Quantum Computing: Progress, Challenges and Outlook, Battistel et al., peer-reviewed review article in Nano Futures 7 032003, 2023.
4. Riverlane's real-time QEC system achieves 10x lower latency than Google's reported results, Riverlane technical update, 9 April 2026.
5. Fault-Tolerant Quantum Computing with Trapped Ions: The Walking Cat Architecture, Tripier et al., arXiv preprint, 22 April 2026.