Building the Feedback Loop for Physical AI

For most of the last decade, AI's biggest breakthroughs have involved large data centers and cloud infrastructure. But a more consequential shift is happening at the same time: Physical AI. Intelligence is increasingly embedded directly into physical systems that must act instantly in our unpredictable world, requiring a fundamentally different approach to compute than traditional cloud or data-center AI. 

These systems must respond to changing conditions, often in real time, with software decisions that carry real-world consequences. A warehouse robot spotting an obstacle or identifying a load too heavy to lift, or a vehicle detecting a pedestrian stepping into its path, must process that information locally within strict timing constraints while balancing performance, power, safety, reliability, and cost. 

That creates a challenge for developers. Physical AI systems need capable hardware, but "capable" is difficult to define in isolation. Standards need to support different workloads, software has to inform hardware design, and developers need platforms built around target workloads. Each layer depends on the other: software, architecture, standards, and developer tools all have to work together. 

That's the premise behind MIPS' approach: a continuous feedback loop, in which developer needs and workload insights shape the standards, architectures, and platforms that come next. 

Starting with Open Standards

Physical AI introduces new requirements around real-time performance, deterministic execution, safety, efficiency, and workload-specific optimization. As a result, architectures must evolve alongside emerging application demands. For many design companies, participation in an open standards ecosystem provides valuable visibility into how the industry is addressing these challenges, from evolving workloads and software requirements to the needs of developers and system designers. This insight helps inform how architectures and broader ecosystems must evolve to support the next generation of intelligent systems. 

In 2021, MIPS announced its decision to embrace RISC-V as the architectural foundation for its next generation of compute solutions. This gave the company an open, flexible foundation on which to build differentiated processor architectures and workload-focused technologies while participating in a broader ecosystem that can help accelerate innovation across Physical AI and other emerging computing markets. 

More than five years later, MIPS remains deeply committed to RISC-V, highlighted by its recent elevation to Premier Member of RISC-V International. MIPS CTO Yankin Tanurhan also serves as vice chairman of the organization, further strengthening MIPS’ role in shaping the RISC-V ecosystem and supporting its position in the Physical AI market. While anyone can build on RISC-V, Premier Membership gives MIPS a seat on the organization’s technical committee, providing a direct role in influencing the evolution of the standard itself. MIPS is now active in several committees, task groups, and Special Interest Groups (SIGs) spanning automotive, functional safety, security, crypto, vector processing, and documentation.

Turning Standards into Hardware

Open standards deliver value when they can be translated into hardware that meets developer needs. MIPS' influential position in the ecosystem helps inform its development of RISC-V-based processor IP and microarchitectures around specific workload characteristics, connecting broader architectural standards with the demands of real-world applications. 

At the microarchitecture level, workload characteristics begin to influence actual hardware decisions: what needs to run efficiently, where a few extra watts of power budget is critical, where latency matters, and how processing tasks are divided internally. For example, workloads that require continuous multi-sensor perception with strict latency constraints may benefit more from tightly coupled memory and efficient data movement than from higher clock speeds alone. 

The MIPS S8200, a RISC-V-based NPU, illustrates this workload-focused approach. Designed around the distinct characteristics of AI inference at the edge, it addresses the need for high-throughput parallel data processing within strict power, thermal, and latency constraints. These considerations are particularly important for edge devices operating on minimal AC power or batteries. In applications such as autonomous vehicle steering, for instance, efficient inference can help systems process sensor data and respond to changing conditions within tight timing requirements. MIPS designed the microarchitecture's execution unit and memory interfaces around these software behaviors, tailoring the hardware to the demands of edge AI inference. 

MIPS Acies platforms. Source: MIPS.

From Processor IP to Workload-native Platforms

Developers need more than hardware to translate Physical AI models into real-world systems. Independently sourcing, integrating, and testing every layer of software, networking, and processor IP can also create unnecessary friction. 

To bridge this gap, MIPS packages its custom RISC-V processor IP into three workload-native Physical AI platforms, which the company launched in September 2026: Acies, Actus, and Aegis. These frameworks allow developers to build around the specific workloads and requirements of their applications. 

• Acies: An inference-native platform for modern edge AI workloads, combining an open, standards-based NPU with an open software stack

• Actus: An event-native platform for real-time embedded applications such as motion control, sensor fusion, and predictive maintenance

• Aegis: A safety-native platform for mission-critical Physical AI systems requiring low latency and agentic processing

While these platforms address different workload characteristics, they all share MIPS’ broader software-first, open, and modular approach. As MIPS CEO Sameer Wasson explained, "MIPS is driving this shift with open, software-first platforms that give customers a common foundation to build, customize, and deploy Physical AI, with efficiency and tokens-per-watt as the foundation of our technology."

Acies, Actus, and Aegis are also production-ready environments designed to support commercial and ecosystem development. A unified software stack, combined with microarchitectures built around specific workload profiles, helps developers scale quickly from prototype to production without having to build software from scratch. 

The Software Layer Closes the Gap

Physical AI workloads evolve rapidly and may combine traditional embedded processing with AI inference, real-time sensing, and other complex functions. At the same time, hardware decisions establish limits on compute power, memory bandwidth, thermal performance, and other critical capabilities. If software isn't considered earlier in the hardware development process, developers risk designing systems around assumptions that don't hold once the software is running. 

MIPS' workload modeling and tools, such as Atlas Explorer, give developers earlier visibility into how software and models will behave on prospective hardware. Engineering teams can create digital twin models that run actual workloads on virtual RISC-V compute subsystems, allowing them to predict latency, instruction execution, and data flow. This environment enables teams to co-design hardware and software from the outset rather than treating software as something that comes after the silicon is finished.

The software-first approach supports system-wide optimization. Developers can pinpoint where a complex blend of sensing and inference creates a bottleneck and identify exactly where the workload may benefit from specialized acceleration. The same modeling environment can reveal where hardware resources aren't being fully utilized, helping engineers make micro-architectural adjustments that can maximize edge metrics like tokens-per-watt.

Enabling the Ecosystem, Not Just the End Product

For RISC-V and Physical AI to reach their full potential, the broader ecosystem - including software developers, semiconductor designers, OEMs, integrators, standards organizations, and other technology partners working around the same architecture - needs open, accessible platforms it can build on, experiment with, and customize. 

MIPS provides rich developer environments and platforms that allow the ecosystem to rapidly prototype, test ideas, and iterate long before committing to production. This approach is supported by a portfolio covering the core layers of the design cycle: processor IP, software and modeling tools, application-specific/custom silicon, and Physical AI platforms. GlobalFoundries (GF) complements these capabilities with process, packaging, and manufacturing expertise.

The MIPS Feedback Loop

MIPS connects open standards, hardware architecture, software, and developer platforms into a continuous feedback loop for Physical AI. Each layer informs the next, creating an iterative development process rather than following a linear path from standards to chips to products. 

• Standards: MIPS contributes to the development of open standards and the architectural foundation for the ecosystem. As developers encounter new edge-processing requirements, those needs can inform the evolution of the RISC-V ISA through industry participation. 

• Microarchitecture: MIPS translates architectural standards into processor designs optimized for specific workloads.

• Platforms: MIPS packages these capabilities into workload-native platforms and development tools, giving developers an environment to build, test, and customize solutions for real-world applications. 

• Developers and ecosystem: Developers use the platforms, identify new requirements, and provide feedback through real-world workloads and applications.

• Back to standards and hardware: That feedback informs future architectural, hardware, and platform development.

This continuous feedback loop is critical for Physical AI, where perception, reasoning, and response may need to happen simultaneously under strict power, latency, reliability, and safety constraints. An autonomous vehicle or industrial robot, for example, may need to process sensor inputs, run transformer inference, and execute safety-critical motor control within the same system. The underlying computing architecture must accommodate these combined requirements as software and workloads evolve. 

The result is a tighter connection between software requirements and hardware development. Developers gain a more direct path from ideas to working systems, enterprises can reduce friction on the path to production, and Physical AI systems can be optimized around the workloads they need to run in the real world. 

What This Could Mean for Physical AI

As AI moves beyond the cloud and data centers into the physical world, it will span different combinations of workload characteristics and deployment environments. From robotics and automotive to industrial and other embedded systems, the next generation of Physical AI will require architectures that accommodate a wide range of processing requirements. 

These systems will demand compute that is configurable enough to adapt to rapidly changing workload combinations, while still satisfying real-world constraints around efficiency, latency, safety, and reliability. 

Meeting these challenges at scale requires industry-wide adoption of open, software-first development models. Software must be co-designed alongside hardware so technology partners can build and adapt computing infrastructure faster and with greater flexibility. MIPS’ workload-native platforms provide an example of how the industry can move from broad architectural standards toward more application-aware computing platforms.

The success of the next stage of RISC-V development will depend not only on defining architectures or adding new extensions, but on building an environment where developers can readily build, test, and deploy systems that can navigate real-world constraints safely and efficiently.