AI Generated Open-Source Silicon Design Challenge
Show the world how innovation can move from prompt to silicon in record time!
Generative AI offers the potential to accelerate chip innovation by putting chip design into the hands of more people than ever before and enabling them to design faster and for less cost.
This Challenge aims to show how a community can use this powerful new tool to deliver interesting designs in a matter of weeks.
The challenge is now open until Friday, June 2, 2023 at 11:59 pm PT.
Use generative AI (e.g. chatGPT, Bard or similar) to generate a complete Verilog model for a digital design. The design must be implemented using chipIgnite that includes an SoC template (Caravel) providing rapid chip-level integration and an open-source RTL-to-GDS digital design flow (OpenLane).
A successful project must provide all prompts used to generate a complete RTL model for the design. In addition, verification testbenches that demonstrate the design meets the intended functionality must be provided and maybe created conventionally.
Participants will be eligible to win free fabrication for their design and receive public recognition and promotion of their design by Efabless. The value of getting your chips made is $9750. Be among one of the first to design and tapeout an AI-generated open-source silicon design!
In addition, each submission that meets the requirements will received a development board with a fabricated chip from one of the winning projects.
How to Enter
Register on the Efabless platform.
Join the challenge channel #generative-ai-silicon-challenge on open-source-silicon.dev Slack space for updates and additional help and resources. Register for the webinar on May 24 @ 9am PST providing an overview and Q&A.
Submit your entry by including all content (including video and screenshots) on a public GitHub repo.
Create a public project for the chipIgnite 2306Q shuttle using the GitHub repo from the previous step.
Submit success precheck and tapeout jobs for your design.
Complete the remainder of the billing and shipping information as well as terms and export agreements. You will not be charged or invoiced for your submission. Complete the final submission for the project on the platform.
Send an email to email@example.com with a link to your project.
Limit one entry per person, per email address. Your entry must be original.
Note: If you have not received permission to use copyrighted material, you may not include the material in your entry.
Learn more about how to enter at the design contest webinar. The event will cover some tips on submitting your project and answer some of the most commonly asked questions about chipIgnite.
Register for the webinar here.
|Challenge opens||Friday, May 19th, 2023|
|Challenge Webinar. Register here.||Wednesday, May 24, 2023, at 09:00 AM, PT|
|Challenge closes||Friday, June 2, 2023, at 11:59 pm PT.|
|Tapeout begins||Monday, June 5th, 2023|
|Public winner announcement||Friday, June 9th, 2023|
All designs will be judged by a panel of experts who share a lifelong commitment to electronics and believe in the power of AI and machine learning to drive innovation. Stay tuned for more details!
Project Description and success in the community interest poll
All requirements must be met to be eligible to win
All submission content, documentation, prompt must be in English.
A short description of the project must be included with your design. It will be used for introducing your idea in the community poll.
All designs must be implemented and fit in the Caravel User Project area.
The Verilog for the design must be coded by AI.
Verification may be done outside of the AI environment but verification testbenches must be provided as a reproducible element of this process.
All prompts or auto GPT session logs used in the design must be provided as part of the deliverables for the design.
The design needs to be open source with all materials required to reproduce made public.
To facilitate reproducibility by the community, the design must be implemented using the OpenLane chipIgnite flow including all configuration and run results.
Must have testbenches for RTL verification as well as constraints for STA and SDF simulations.
Must be implementable in SKY130 with available standard cells and DFFRAM and not require open RAM or other discrete memories for implementation.
The design must pass precheck and tapeout submissions on the Efabless platform.
Winners will be expected to provide a video and screenshots demonstrating the creation of the project in a how-to or step-by-step format. These materials may be used by Efabless for promotional purposes.
Please contact firstname.lastname@example.org if you have any questions about this contest. Join the Slack channel to learn more and vote in the community poll.